MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1665

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix B
Revision History
This appendix provides a list of major differences between revisions of the MPC8536E PowerQUICC III
Integrated Processor Reference Manual.
B.1
Major changes from Revision 0 to Revision 1 are as follows:
Section/Page
4.3.1.1.2, 4-5
4.4.4.1, 4-25
4.4.4.2, 4-25
5.3.1, 5-6
8.3.2, 8-7
8.4.1.9, 8-26
Freescale Semiconductor
Changes From Revision 0 to Revision 1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Added clarification for CCSRBAR[BASE_ADDR] as follows:
Replaced phrase “identifies the16 most-significant address bits of the window”
with “identifies the16 most-significant address bits of the 36-bit window.”
Added the following sentence to second paragraph:
“If the separate (asynchronous) PCI_CLK clock signal is used rather than
SYSCLK as the PCI clock, then this clock must be constantly driven, even when
in Deep Sleep mode in order to avoid loss of lock.”
Added the following sentence to end of section:
“For any SerDes that is not disabled through cfg_io_ports[0:2]=001 or
cfg_srds2_prtcl[0:2]=111 respectively, the applicable
SDn_REF_CLK/SDn_REF_CLK must be constantly driven, even when in Deep
Sleep mode, in order to avoid loss of lock.”
Updated SVR values in Table 5-2, “Device Revision Level Cross-Reference,” as
follows:
0x803F_0091 for MPC8536E Rev 1.1 (with security)
0x8037_0091 for MPC8536 Rev 1.1 (without security).
Changed signal description of MA[
Assertion/Negation—The address is always driven when the memory controller is
enabled. It is valid when a transaction is driven to DRAM (when MCS is active).
to:
Assertion/Negation—The address lines are only driven when the controller has a
command scheduled to issue on the address/CMD bus; otherwise they will be at
high-Z. It is valid when a transaction is driven to DRAM (when MCS is active).
Updated DDR_SDRAM_CFG_2[DQS_CFG] field description to designate a
value of 0x0 as reserved. (Note that since the the default value for this field is
reserved, software must configure this field to a valid value during initialization.)
Changes
15:0
] from:
B-1