MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 472

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Table 10-15
simultaneously. Whenever an error field bit is set a channel error interrupt is generated, and in most cases
the channel is halted. For some error types, the host must take action to clear the error bit before restarting
the channel, as described in
of the R and CON bits in
10-42
16–22
23–31
32–34
35–39
48–59
60–63
40-43
9–15
Bits
44
45
46
47
8
lists the errors corresponding to each bit in the CSR’s Error field. Multiple bits may be set
MAIN_STATE
PUT_STATE
FF_LEVEL
Name
Error
PRD
SRD
PD
SD
—
—
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-14. Channel Status Register Field Descriptions
Section 10.4.4.1, “Channel Configuration Register
Reserved.
Put state machine state. This field reflects the state of the put state machine when it last
went to sleep, or the state captured when an error occurred. For debug purposes only.
Reserved.
Main state machine state. This field reflects the state of the main state machine when it last
went to sleep, or the state captured when an error occurred. For debug purposes only.
Reserved, should be set to zero.
Fetch FIFO level. This five-bit counter indicates how many pointers are currently stored in
the fetch FIFO.
Reserved, should be set to zero.
Primary EU reset done. This bit reflects the state of the reset done signal from the assigned
primary EU.
0 The assigned primary EU reset done signal is inactive.
1 The assigned primary EU reset done signal is active, indicating its reset sequence has
Secondary EU reset done. This bit reflects the state of the reset done signal from the
assigned secondary EU.
0 The assigned secondary EU reset done signal is inactive.
1 The assigned secondary EU reset done signal is active, indicating its reset sequence
Primary EU done. This bit reflects the state of the done interrupt from the assigned
primary EU.
0 The assigned primary EU done interrupt is inactive.
1 The assigned primary EU done interrupt is active, indicating the EU has completed
Secondary EU done. The SEC_DONE bit reflects the state of the done interrupt from the
secondary EU.
0 The assigned secondary EU done interrupt is inactive.
1 The assigned secondary EU done interrupt is active, indicating the EU has completed
Error bits for the channel. See
Reserved.
Table
completed and it is ready to accept data.
has completed and it is ready to accept data.
processing and final values are available from EU registers. If the EU has an output
FIFO, then all text data output has been placed in the output FIFO. If the EU provides
context out through the output FIFO, then the context is placed in the output FIFO after
the PD bit is asserted.
assigned
processing and final values are available from EU registers.
10-15. For information about restarting the channel, see the description
Figure
10-15.
Description
(CCR)”.
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