MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1205

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4.1.10.2 PCI Express Controller Internal Interrupt Sources
Table 17-125
preconditions for signaling the interrupt.
Freescale Semiconductor
Any bit in PEX_PME_MES_DR set
Any bit in PEX_ERR_DR set
PCI Express Root Status Register[16]
(PME status) is set
PCI Express Root Error Status Register[6]
(fatal error messages received) is set
PCI Express Root Error Status Register [5]
(non-fatal error messages received) is set
PCI Express Root Error Status Register[0]
(correctable error messages received) is set
Any correctable error status bit in PCI Express
Correctable Error Status Register is set
Any fatal uncorrectable error status bit in PCI
Express Uncorrectable Error Status Register is
set. (The corresponding error is classified as
fatal based on the severity setting in PCI
Express Uncorrectable Error Severity Register.)
Any non-fatal uncorrectable error status bit in
PCI Express Uncorrectable Error Status
Register is set. (The corresponding error is
classified as non-fatal based on the severity
setting in PCI Express Uncorrectable Error
Severity Register.)
PCI Express Secondary Status Register[8]
(master data parity error) is set.
PCI Express Secondary Status Register[11]
(signaled target abort) is set
PCI Express Secondary Status Register[12]
(received target abort) is set
Status Register Bit
describes the sources of the PCI Express controller internal interrupt to the PIC and the
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-125. PCI Express Internal Controller Interrupt Sources
PCI Express Root Control Register [3] (PME interrupt enable) is set
PCI Express Root Error Command Register [2] (fatal error reporting enable)
is set
or
PCI Express Root Control Register [2] (system error on fatal error enable) is
set
PCI Express Root Error Command Register [1] (non-fatal error reporting
enable) is set
or
PCI Express Root Control Register [1] (system error on non-fatal error
enable) is set
PCI Express Root Error Command Register[0] (correctable error reporting
enable) is set
or
PCI Express Root Control Register[0] (system error on correctable error
enable) is set.
The corresponding error mask bit in PCI Express Correctable Error Mask
Register is clear and PCI Express Root Error Command Register[0]
(correctable error reporting enable) is set
The corresponding error mask bit in PCI Express Uncorrectable Error Mask
Register is clear and either PCI Express Device Control Register[2] (fatal
error reporting) is set or PCI Express Command Register[8] (SERR) is set.
The corresponding error mask bit in PCI Express Uncorrectable Error Mask
Register is clear
and
either PCI Express Device Control Register[1] (non-fatal error reporting) is set
or PCI Express Command Register[8] (SERR) is set.
PCI Express Secondary Status Interrupt Mask Register[0] (mask master data
parity error) is cleared and PCI Express Command Register[6] (parity error
response) is set.
PCI Express Secondary Status Interrupt Mask Register[1] (mask signaled
target abort) is cleared.
PCI Express Secondary Status Interrupt Mask Register[2] (mask received
target abort) is cleared.
The corresponding interrupt enable bits must be set in PEX_PME_MES_IER
The corresponding interrupt enable bits must be set in PEX_ERR_EN.
Preconditions
PCI Express Interface Controller
17-109