MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1699

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Index
PCI_AD[63:0] (PCI address/data bus) signals, 16-6
PCI_C/BE[7:0] (PCI command/byte enable) signals, 16-7,
PCI_DEVSEL (PCI device select) signal, 16-7, 16-48
PCI_FRAME (PCI frame) signal, 16-7, 16-45
PCI_GNT[4:0] (PCI bus grant) signals, 16-8, 16-42
PCI_IDSEL (PCI initialization device) signal, 16-8
PCI_IRDY (PCI intitiator ready) signal, 16-8, 16-45
PCI_PAR (PCI parity) signal, 16-9
PCI_PERR (PCI parity error) signal, 16-9, 16-66
PCI_REQ[4:0] (PCI bus request) signals, 16-9, 16-42
PCI_SERR (PCI system error) signal, 16-10, 16-66
PCI_STOP (PCI stop) signal, 16-10, 16-49
PCI_TRDY (PCI target ready) signal, 16-10, 16-45, 16-52
Performance monitor (device)
Freescale Semiconductor
turnaround cycle, 16-49
block diagram, 24-2
burstiness, 24-14, 24-28
control registers, 24-5–24-10
counters (PMCn)
event counting, 24-12
events, 24-16–24-27, ??–24-27
events triggered by watchpoint monitor, 25-26
examples, 24-27
fast back-to-back transactions, 16-56
interrupt-acknowledge transactions, 16-63
read transactions, 16-50
retry transactions, 16-53
special-cycle transactions, 16-64
timing diagrams, 16-50
transaction termination, 16-52
write transactions, 16-50, 16-51
16-46, 16-48, 16-49, 16-65
chaining, 24-13
registers, 24-10
triggering, 24-13
chaining, 24-27
DDR controller, 24-17
debug, 24-26
DMA controller, 24-18
DUART, 24-26
e500 coherency module (ECM), 24-19
interrupt controller (PIC), 24-21
L2 cache/SRAM, 24-26
local bus controller (LBC), 24-26
PCI/PCI-X common events, 24-21
burstiness event, 24-14
bus status register, termination status, 16-54
completion, 16-53
master-abort termination, 16-53
master-initiated, 16-52
target-initiated, 16-53, 16-54
timeout, 16-53
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Phase-locked loops (PLLs)
PHY clocks, 21-4
PHY interface, 21-41
PKEU
Power management
Power-on reset (POR)
external signals, 24-3
features, 24-3
functional description, 24-11
interrupts, 24-11
interrupts (from PIC) to generate events, 9-32
masking interrupts (from PIC), 9-32
memory map/register definition, 24-3
overflow indication on TRIG_OUT, 25-24
overview, 24-2
threshold events, 24-12
POR status (global utilities), 23-5
data size register, 10-149
EU_GO register, 10-96, 10-116, 10-143, 10-154, 10-160
interrupt control register, 10-153
interrupt status register, 10-151
key size register, 10-147, 10-148
mode register, 10-147
parameter memory A, 10-154
parameter memory B, 10-155
parameter memory E, 10-155
parameter memory N, 10-155
reset control register, 10-149
status register, 10-112, 10-150
block disable
DDR interface, 8-80
device low-power modes, 23-47–??
PCI Express, 17-13–17-18, 17-69–17-70
PCI special-cycle operations, 16-64
see also Global utilities, power management
configuration
burstiness event counting, 24-28
simple event counting, 24-27, 24-28
threshold event counting, 24-28
triggering event counting, 24-27, 24-28
block disable control (DEVDISR), 23-16
control and status register (POWMGTCSR), 23-19,
READY negation, 4-2
boot ROM location, 4-14
boot sequencer configuration, 4-18
clock
CPU boot configuration, 4-17
DDR debug mode (ECC pins used for debug), 4-23, 25-3
eTSEC1 protocol, 4-21
e500 core PLL ratio, 4-12
system/CCB PLL ratio, 4-11
23-21
Index-13
P–P