MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1650

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Complete List of Configuration, Control, and Status Registers
A-38
0x00C0–
0x1040–
0x00A0
0x00B0
0x0FF0
0x10A0
0x10B0
0x10C0
0x10D0
0x10E0
0x11A0
0x10F0
0x0040
0x0050
0x0060
0x0070
0x0080
0x0090
0x1000
0x1010
0x1020
0x1030
0x1070
0x1080
0x1090
0x1100
0x1110
0x1120
0x1130
0x1140
0x1150
0x1160
0x1170
0x1180
0x1190
Offset
IPIDR0—Interprocessor interrupt 0 (IPI 0) dispatch register
IPIDR1—IPI 1 dispatch register
IPIDR2—IPI 2 dispatch register
IPIDR3—IPI 3 dispatch register
CTPR—Current task priority register
WHOAMI—Who am I register
IACK—Interrupt acknowledge register
EOI—End of interrupt register
Reserved
FRR—Feature reporting register
Reserved
GCR—Global configuration register
Reserved
Vendor reserved
VIR—Vendor identification register
PIR—Processor core initialization register
IPIVPR0—IPI 0 vector/priority register
IPIVPR1—IPI 1 vector/priority register
IPIVPR2—IPI 2 vector/priority register
IPIVPR3—IPI 3 vector/priority register
SVR—Spurious vector register
TFRRA—Timer frequency reporting register (Group A)
GTCCRA0—Global timer 0 current count register (Group A)
GTBCRA0—Global timer 0 base count register (Group A)
GTVPRA0—Global timer 0 vector/priority register (Group A)
GTDRA0—Global timer 0 destination register (Group A)
GTCCRA1—Global timer 1 current count register (Group A)
GTBCRA1—Global timer 1 base count register (Group A)
GTVPRA1—Global timer 1 vector/priority register (Group A)
GTDRA1—Global timer 1 destination register (Group A)
GTCCRA2—Global timer 2 current count register (Group A)
GTBCRA2—Global timer 2 base count register (Group A)
GTVPRA2—Global timer 2 vector/priority register (Group A)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PIC Global Registers—Block Base Address 0x4_0000
Table A-14. PIC Global Registers (continued)
Register
Global Timer Group A Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
—
—
—
—
R
R
R
R
R
R
R
0x006B_0 n 020
0x0000_FFFF
0x0000_0000
0x0000_000F
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x8000_0000
0x0000_0000
0x0000_0000
0x8000_0000
0x8000_0000
0x0000_0001
0x0000_0000
0x8000_0000
0x8000_0000
0x0000_0001
0x0000_0000
0x8000_0000
0x8000_0000
x0067_0002
Reset
n/a
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Freescale Semiconductor
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