MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 258

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
L2 Look-Aside Cache/SRAM
Table 6-28
L2. The transaction types and attributes listed follow MPX bus nomenclature, with the addition of write
allocate (burst write with L2 cache allocation).
pushes triggered by snoops, listed in
6-38
dcbf
dcbst
icbi
Source of Transaction
Read, snoop local processor
Read, unlock L2 cache line
Write
Write <
Write, allocate L2 cache line 32-byte
Write, allocate L2 cache line < 32-byte I/T
Write, allocate and lock L2 cache line
32-byte
Write, allocate and lock L2 cache line
< 32-byte
ATOMIC increment, decrement, set,
and clear
32-byte
lists L2 cache state transitions for all system-initiated (non-core) transactions that change the
32-byte
Transaction Type
Table 6-27. State Transitions Due to Core-Initiated Transactions (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 6-28. State Transitions Due to System-Initiated Transactions
Initial States
dL1
iL1
I,E
I,V
L1
E/EL/T
E/EL/T
Table
I/T
E
EL
I/T
E/EL
I/E/EL/T
I
E/EL
T
I/E/EL/T
I/E
EL/T
I/T
E/EL
E/EL
I/E
EL/T
E/EL
I/E/EL/T
I/T
E/EL
I/E
EL/T
L2
I/
I/
Initial L2
State
6-27.
Hit
No
No
L2
Table 6-28
Same
E
EL
I
E
I
E
Same
EL
EL
I
T
Same
Same
EL
E
EL
Same
Same
EL
Same
EL
I
T
Final States
L1
Final L2
I
I
State
L2
I
I
accounts for changes caused by L1 snoop
Miss in cache external write (CEW) windows
Hit in CEW window
Hit in CEW window (CEW lock attribute set)
Miss in CEW windows
Hit in CEW window (no data is written)
(regardless of CEW lock attribute)
Hit in CEW window
Hit in CEW window (CEW lock attribute set)
Allocate regardless of CEW window
No data is written
Allocate and lock regardless of CEW window
No data is written
Invalidate line
Invalidate data, keep lock
Comments
Comments
Freescale Semiconductor

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