MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1266

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
threshold takes into consideration the latency involved in getting the far end to stop transmitting the data.
This threshold is programmable to allow for the use of high-latency repeaters or retainers in between the
host and device.
The transmit FIFO is written with data to be sent in the FIS transferred by the DMA controller. When the
data is stable at the output of the transmit FIFO, the link layer can take the data. If the transmit FIFO cannot
supply data to the link layer, the transport layer stalls the link layer, which will in turn send HOLD
primitives to the far end.
19.5
Link Layer Overview
The function of the SATA link layer is to interface between the transport and physical layers in the
transmission and reception of frames and primitives. The link layer utilizes the two unidirectional links
provided by the SATA interface to maintain coordinated communication between the host and the device.
Payload data can only be transmitted in one direction at a time. The link layer can work at either SATA
first-generation (1.5 Gbps) or second-generation 2 (3 Gbps) speeds.
On transmit, the link layer first communicates with the peer far end link layer to determine if it is ready to
receive. Assuming the far end link layer can receive data, the local link layer can then begin to take data
in the form of words from its transport layer. It inserts start-of-frame (SOF) before the start of the data
portion of a frame, calculates and inserts the CRC after the data portion of a frame, and inserts the EOF
primitive at the end. The link layer scrambles the contents of the frame, including the calculated CRC, but
excluding the SOF and EOF diameters and any other embedded primitives. The 8B/10B encoding of the
data is done in the PHY layer. At the end of the transmission, the link layer reports transmission status to
the transport layer.
On receive, the link layer first acknowledges its readiness to receive with its peer link layer. Then it awaits
reception of the SOF primitive that marks the start of the received data. Following detection of the SOF
primitive, the link layer proceeds to accept the incoming data. The 8B/10B decoding of the data is done in
the PHY layer. Next, the link layer removes all primitives including the SOF and EOF diameters. It then
descrambles the contents of the frame. The link layer also calculates the CRC on the incoming frame
between the SOF and EOF delimiters, and compares this calculated value to the received value. Any
mismatch is reported to the transport layer. During frame reception, disparity or code errors are reported
to the command layer, and appropriate action is taken in the link layer. The descrambled and decoded
receive data stream is passed to the transport layer as the frame is being received. Finally, at the end of the
frame, the link layer reports reception status to the transport layer.
The link layer also partakes in flow control between the local and remote ends. The layer supports flow
control actions based on the local FIFO status (located in the transport layer), or in response to receiving
flow control messages from the remote end.
The transmit side of the link layer is also responsible for inserting a pair of ALIGN primitives every 254
words, or more frequently if programmed by the user.
19.5.1
Link Layer functionality
The link layer is composed of a number of functions:
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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Freescale Semiconductor