MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1371

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.24 Age Count Threshold Register (AGE_CNT_THRESH)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The age
count threshold (AGE_CNT_THRESH) register provides the aging counter threshold value used to
determine the priority state of the USB controller’s internal system interface.It is only enabled if
PRI_CTRL[pri_en] = 1. The threshold value is in units of platform clock/2 cycles. This register should be
written during system initialization or during normal system operation when the system bus interface is
idle. It can be read at any time.
If the aging counter is less than the AGE_CNT_THRESH value, default (low) priority is chosen If the
aging counter is greater than or equal to the AGE_CNT_THRESH value and PRI_CTL[pri_en] = 1, an
elevated priority is chosen
The aging counter begins to count from zero when a bus access is requested. It increments every bus cycle
until the bus transaction completes. At the completion of a bus transaction, the counter is synchronously
reset to zero. If there are any outstanding bus requests, the aging counter will then begin counting
immediately.
The AGE_CNT_THRESH is compared against the value of the aging counter during each clock cycle of
the current transaction. If AGE_CNT_THRESH is equal to zero, an elevated priority is always chosen. If
the aging counter is less than the AGE_CNT_THRESH value, default (low) priority is selected. If the
aging counter is greater than or equal to the AGE_CNT_THRESH value and PRI_CTL[pri_en] = 1, an
elevated priority is chosen.
Freescale Semiconductor
20–26
27–31
0–19
Bits
Snoop address
Snoop Enables
Name
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
The starting base address for which transactions are snooped.
Reserved, should be cleared
0x00 Snooping disabled
0x0B 4-Kbyte snoop range starting at the value defined by SNOOP n [0–19]
0x0C 8-Kbyte snoop range starting at the value defined by SNOOP n [0–18]
0x0D 16-Kbyte snoop range starting at the value defined by SNOOP n [0–17]
0x0E 32-Kbyte snoop range starting at the value defined by SNOOP n [0–16]
0x0F 64-Kbyte snoop range starting at the value defined by SNOOP n [0–15]
0x10 128-Kbyte snoop range starting at the value defined by SNOOP n [0–14]
0x11 256-Kbyte snoop range starting at the value defined by SNOOP n [0–13]
0x12 512-Kbyte snoop range starting at the value defined by SNOOP n [0–12]
0x13 1-Mbyte snoop range starting at the value defined by SNOOP n [0–11]
0x14 2-Mbyte snoop range starting at the value defined by SNOOP n [0–10]
0x15 4-Mbyte snoop range starting at the value defined by SNOOP n [0–9]
0x16 8-Mbyte snoop range starting at the value defined by SNOOP n [0–8]
0x17 16-Mbyte snoop range starting at the value defined by SNOOP n [0–7]
0x18 32-Mbyte snoop range starting at the value defined by SNOOP n [0–6]
0x19 64-M byte snoop range starting at the value defined by SNOOP n [0–5]
0x1A 31-Mbyte snoop range starting at the value defined by SNOOP n [0–4]
0x1B 256-Mbyte snoop range starting at the value defined by SNOOP n [0–3]
0x1C 512-Mbyte snoop range starting at the value defined by SNOOP n [0–2]
0x1D 1-Gbyte snoop range starting at the value defined by SNOOP n [0–1]
0x1E 2-Gbyte snoop range starting at the value defined by SNOOP n [0]
Table 21-31. SNOOP n Register Field Descriptions
Description
Universal Serial Bus Interfaces
21-37