MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 207

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4-11
Freescale Semiconductor
0x4C–0x4F
0x5C–0x5F
0x00–0x3F
0x40–0x43
0x44–0x47
0x48–0x4B
0x50–0x53
0x54–0x57
0x58–0x5B
Address
shows the required eSPI EEPROM data structure.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved.
BOOT signature. This location should contain the value 0x424f_4f54, which is the ascii code for
BOOT. The eSPI loader code will search for this signature, initially in 24-bit addressable mode. If
the value in this location doesn't match the BOOT signature, then the EEPROM is accessed again,
but in 16-bit mode. If the value in this location still doesn’t match the BOOT signature, it means
that the eSPI device doesn't contain a valid user code. In such case the eSPI loader code will
disable the eSPI and will issue a hardware reset request of the SoC by setting
RSTCR[HRESET_REQ].
Reserved
User’s code length. Number of bytes in the user’s code to be copied.
Must be a multiple of 4.
4<=User’s code length <= 2GBytes.
Reserved
Source Address. Contains the starting address of the user’s code as an offset from the EEPROM
starting address. In 24-bit addressing mode, the 8 most significant bits of this should be written to
as zero, because the EEPROM is accessed with a 3-byte (24-bit) address. In 16-bit addressing
mode, the 16 most significant bits of this should be written to as zero.
Reserved
Target Address. Contains the target address in the system’s local memory address space in which
the user’s code will be copied to. This is a 32-bit effective address. The core is configured in such
a way that the 36-bit real address is equal to this (with 4 most significant bits zero).
Reserved
Figure 4-11. eSPI EEPROM Data Structure
Table 4-38. eSPI EEPROM Data Structure
0x6C
0x3F
0x6B
0x7F
0x00
0x40
0x80
Configuration Words
Control Words
User’s Code
Reserved
Reserved
•
•
•
Data Bits [0:31]
Source Address
Reset, Clocking, and Initialization
4-37