MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 863

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-70
14.5.3.7
This section provides detailed descriptions of the registers used for hash functions. All of the registers are
32 bits wide. The DA field of every received frame is processed through a 32-bit CRC generator (CRC-32
polynomial), and the 8 or 9 most significant bits of the CRC are mapped to a hash table entry. The user
can enable a hash entry by setting its bit. A hash entry usually represents a set of addresses. A hash table
hit occurs if the DA CRC result points to an enabled hash entry. Software may need to further filter the
address in order to eliminate false-positive hits in the hash table.
If RCTRL[GHTX] = 0, the 8 most significant bits of the CRC are used as the hash table index. In this case,
registers IGADDR0–IGADDR7 comprise a 256-entry hash table exclusively for individual (unicast)
address matching, while registers GADDR0–GADDR7 comprise a 256-entry hash table for group
(multicast) address matching. If RCTRL[GHTX] = 1, the group hash table is extended to all 512 entries,
and the 9 most significant bits of the CRC are used as the hash table index. In this case, registers
IGADDR0–IGADDR7 hold hash table entries 0–255 for group addresses, while registers
GADDR0–GADDR7 hold entries 256–511 of the extended group hash table.
See
14.5.3.7.1
The IGADDRn registers are written by the user. Together these registers represent, depending on
RCTRL[GHTX], either the 256 entries of the individual address hash table, or the first 256 entries of the
extended group address hash table used in the address recognition process. The user can enable a hash
entry by setting the appropriate bit. A hash table hit occurs if the DA CRC-32 result points to an enabled
hash entry.
Figure 14-103
Freescale Semiconductor
10–31
Bits
0–9
Offset eTSEC1:0x2_4800+4 n ;
Reset
Section 14.6.3.7.2, “Hash Table Algorithm,”
W
R
eTSEC3:0x2_6800+4 n
Name
RREJ
0
—
describes the fields of the RREJ register.
Hash Function Registers
describes the definition for the IGADDRn register.
Individual/Group Address Registers 0–7 (IGADDR n )
Reserved
Receive filer rejected packet counter. Increments for each frame with valid CRC received, but rejected by
the receive queue filer—either due to a matching rule that asserted the REJ flag or due to filing to a RxBD
ring that was not enabled (see IEVENT[FIQ] error).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-103. IGADDR n Register Definition
Table 14-106. RREJ Field Descriptions
for more information on the hash algorithm.
IGADDR n
All zeros
Description
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
14-115
31