MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1602

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
Table 25-19
25.3.2.6
The trace buffer access control register (TBACR) enables software to read or write the trace buffer. Each
entry is 64 bits; therefore, it takes one write of TBACR and two reads of the access data register (TBADR
and TBADHR) to read one 256-entry array entry. Similarly, it takes one write of TBACR and two writes
of TBADR and TBADHR to write one array entry. Software can access any entry by writing the
appropriate index into TBACR[INDX]. To read or write the buffer sequentially, starting with entry 0, the
index must start with a value of 0 and increment every time a new entry is accessed.
TBACR is shown in
25-20
24–31
4–23
Bits
Offset 0x060
Reset
0
1
2
3
W
R
RD
C_INDX Current index. Represents the current value of the write pointer at the time TBSR was read. This value
0
WRAP
Name
TRIG
ACT
STP
—
describes the TBSR fields.
Trace Buffer Access Control Register (TBACR)
WR
1
Active. Indicates trace buffer activity.
0 The start triggering event has not yet occurred. Trace buffer is not armed.
1 The start triggering event has occurred. Trace buffer is armed.
Triggered. Indicates whether or not a programmed event has been triggered.
0 The programmed event in TBCR0 has not yet been triggered.
1 The programmed event in TBCR0 has been triggered at least once.
Stopped. Indicates whether or not a trace buffer stop condition has been detected.
0 No stop condition yet detected.
1 The trace buffer has detected a stop condition and is no longer capturing events.
Wrapped. Indicates that the trace buffer write pointer has wrapped to the beginning of the buffer at least
once. Set when the last entry of the trace buffer is written.
0 Pointer has not yet wrapped.
1 Pointer has wrapped to the beginning at least once.
Reserved
may be written by software to initialize the write pointer; however, software is not allowed to write the write
pointer while the trace buffer is active. Writes are ignored while the trace buffer is active. It is recommended
to write the status register before enabling the trace buffer in order to zero out any bits that might have
been set during a prior run and to initialize the write pointer to zero.
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
Figure 25-14. Trace Buffer Access Control Register (TBACR)
25-14.
Table 25-19. TBSR Field Descriptions
—
All zeros
Description
23 24
Freescale Semiconductor
Access: Read/Write
INDX
31