MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 310

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.4.1.18
The DDR SDRAM timing configuration 4 register, shown in
required to support DDR3 memories.
Table 8-24
8-36
Bits
0–3
4–7
Offset 0x160
Reset
W
R
Name
describes the TIMING_CFG_4 fields.
RWT
WRT
0
DDR SDRAM Timing Configuration 4 (TIMING_CFG_4)
RWT
Figure 8-19. DDR SDRAM Timing Configuration 4 Register (TIMING_CFG_4)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3
Read-to-write turnaround for same chip select. Specifies how many cycles are added between a read
to write turnaround for transactions to the same chip select. If a value of 0000 is chosen, then the DDR
controller uses the value used for transactions to different chip selects, as defined in
TIMING_CFG_0[RWT]. This field can be used to improve performance when operating in burst-chop
mode by forcing transactions to the same chip select to use extra cycles, while transaction to different
chip selects can utilize the tri-state time on the DRAM interface. Regardless of the value that is set in
this field, the value defined by TIMING_CFG_0[RWT] also is met before issuing a write command.
0000 Default
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Write-to-read turnaround for same chip select. Specifies how many cycles are added between a write
to read turnaround for transactions to the same chip select. If a value of 0000 is chosen, then the DDR
controller uses the value used for transactions to different chip selects, as defined in
TIMING_CFG_0[WRT]. This field can be used to improve performance when operating in burst-chop
mode by forcing transactions to the same chip select to use extra cycles, while transaction to different
chip selects can utilize the tri-state time on the DRAM interface. Regardless of the value that is set in
this field, the value defined by TIMING_CFG_0[WRT] also is met before issuing a read command.
0000 Default
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
4
WRT
Table 8-24. TIMING_CFG_4 Field Descriptions
7
8
RRT
11 12
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
WWT
All zeros
15 16
Description
Figure
8-19, provides additional timing fields
—
Access: Read/Write
Freescale Semiconductor
29
DLL_LOCK
30
31