MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 810

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-33
14-62
Offset eTSEC1:0x2_4330;
Reset
10–15
16–17
18–23
\
Bits
0–1
2–7
8–9
W
R
eTSEC3:0x2_6330
B0CTL
0
B0OFFSET Offset relative to the header defined by B0CTL that locates byte 0 of property ARB. An effective offset
B1OFFSET Offset relative to the header defined by B1CTL that locates byte 1 of property ARB. An effective offset
B2OFFSET Offset relative to the header defined by B2CTL that locates byte 2 of property ARB. An effective offset
1
B0CTL
B1CTL
B2CTL
Name
describes the RBIFX register.
2
B0OFFSET
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Location of byte 0 of property ARB.
00 Byte 0 is not extracted, and appears as zero in property ARB.
01 Byte 0 is located in the received frame at offset (B0OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Location of byte 1 of property ARB.
00 Byte 1 is not extracted, and appears as zero in property ARB.
01 Byte 1 is located in the received frame at offset (B1OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B1OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B1OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Location of byte 2 of property ARB.
00 Byte 2 is not extracted, and appears as zero in property ARB.
01 Byte 2 is located in the received frame at offset (B2OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B2OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B2OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Ethernet DA. In non-FIFO modes, a negative effective offset points to bytes of the standard Ethernet
preamble. Values of B0OFFSET less than 8 are reserved in FIFO modes.
the layer 2 header.
the layer 3 header.
Ethernet DA. In non-FIFO modes, a negative effective offset points to bytes of the standard Ethernet
preamble. Values of B1OFFSET less than 8 are reserved in FIFO modes.
the layer 2 header.
the layer 3 header.
Ethernet DA. In non-FIFO modes, a negative effective offset points to bytes of the standard Ethernet
preamble. Values of B2OFFSET less than 8 are reserved in FIFO modes.
the layer 2 header.
the layer 3 header.
7
B1CTL
8
Figure 14-28. RBIFX Register Definition
Table 14-33. RBIFX Field Descriptions
9
10
B1OFFSET
All zeros
15 16
B2CTL
Description
17 18
B2OFFSET
23 24
B3CTL
Freescale Semiconductor
25 26
Access: Read/Write
B3OFFSET
31