MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1681

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N
Freescale Semiconductor
Medium-dependent interface (MDI) sublayer. Sublayer that defines different connector
Memory access ordering. The specific order in which the processor performs load and
Memory-mapped accesses. Accesses whose addresses use the page or block address
Memory coherency. An aspect of caching in which it is ensured that an accurate view of
Memory consistency. Refers to agreement of levels of memory with respect to a single
Memory management unit (MMU). The functional unit that is capable of translating an
Modified/exclusive/invalid (MEI).
Modified state. MEI state (M) in which one, and only one, caching device has the valid
Most-significant bit (msb). The highest-order bit in an address, registers, data element, or
Most-significant byte (MSB). The highest-order byte in an address, registers, data
NaN. An abbreviation for not a number; a symbolic entity encoded in floating-point
No-op. No-operation. A single-cycle operation that does not affect registers or generate
MPC83536E PowerQUICC™ III Integrated Processor Reference Manual, Rev. 1
types for different physical media and PMD devices.
store memory accesses and the order in which those accesses complete.
translation mechanisms provided by the MMU and that occur externally with the
bus protocol defined for memory.
memory is provided to all devices that share system memory.
processor and system memory (for example, on-chip cache, secondary cache, and
system memory).
effective (logical) address
mechanisms, and defining caching methods.
different devices that share a memory system. Note that neither the PowerPC ISA
nor the Power ISA definitions specifies the implementation of an MEI protocol to
ensure cache coherency.
data for that address. The data at this address in external memory is not valid.
instruction encoding.
element, or instruction encoding.
format. There are two types of NaNs—signaling NaNs and quiet NaNs.
bus activity.
to a physical address, providing protection
Cache coherency
protocol used to manage caches on
Glossary-5