MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1318

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
These three wake-up events (or wake-up interrupts) can be also used to wake up the system from
low-power modes.
20.5.7.1
For the eSDHC to respond to a wake up event, the software must set the respective wake up enable bit
before the CPU enters sleep mode. Refer to
more information on the wakeup enable bits.
Before the software disables the host clock, it should ensure that all of the following conditions have been
met:
20.6
All communication between system and cards are controlled by the host. The host sends commands of two
types: broadcast and addressed (point-to-point) commands.
Broadcast commands are intended for all cards, such as GO_IDLE_STATE, SEND_OP_COND,
ALL_SEND_CID, etc. In broadcast mode, all cards are in the open-drain mode to avoid bus contention.
Refer to
After the broadcast command CMD3 is issued, the cards enter standby mode. Addressed type commands
are used from this point. In this mode, the SDHC_CMD/SDHC_DAT I/O pads turn to push-pull mode, to
have the driving capability for maximum frequency operation. Refer to
MMC/SD,”
20.6.1
Assuming data type WORD is an unsigned 32-bit integer, the below flow is a guideline for sending a
command to the card(s):
send_command(cmd_index, cmd_arg, other requirements)
{
WORD wCmd; // 32-bit integer to make up the data to write into the XFERTYP register, it is
wCmd = (<cmd_index> & 0x3f) << 24; // set the first 8 bits as ‘00’+<cmd_index>
20-44
•
•
•
•
No read or write transfer is active
Data and command lines are not active
No interrupts are pending
Internal data buffer is empty
Section 20.6.5, “Commands for MMC/SD,”
Initialization/Application Information
// recommended to implement in a bit-field manner
Command Send and Response Receive Basic Operation
for the commands of ac and adtc categories.
Setting Wake Up Events
To make the interrupt as wakeup event when all the clocks to eSDHC are
disabled or when whole system is in low power mode, the corresponding
wakeup enable bit need to be set. Refer to
Register (PROCTL),”
register.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
for more information on the eSDHC PROCTL
Section 20.4.8, “Protocol Control Register (PROCTL),”
NOTE
for the commands of bc and bcr categories.
Section 20.4.8, “Protocol Control
Section 20.6.5, “Commands for
Freescale Semiconductor
for