MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1375

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DMA controller must access both control information and packet data from system memory. The
control information is contained in link list–based queue structures. The DMA controller has state
machines that are able to parse data structures defined in the EHCI specification. In host mode, the data
structures are EHCI compliant and represent queues of transfers to be performed by the host controller,
including the split-transaction requests that allow an EHCI controller to direct packets to FS and LS
devices. In device mode, the data structures are designed to be similar to those in the EHCI specification
and are used to allow device responses to be queued for each of the active pipes in the device.
21.4.3
The FIFO RAM controller is used for context information and to control FIFOs between the protocol
engine and the DMA controller. These FIFOs decouple the system processor/memory bus requests from
the extremely tight timing required by USB.
The use of the FIFO buffers differs between host and device mode operation. In host mode, a single data
channel is maintained in each direction through the buffer memory. In device mode, multiple FIFO
channels are maintained for each of the active endpoints in the system.
In host mode, the USB DR module uses a 512-byte Tx buffer and a 512-byte Rx buffer. Device operation
uses a single 512-byte Rx buffer and a 512-byte Tx buffer for each endpoint. The 512-byte buffers allow
the module to buffer a complete HS bulk packet.
21.4.4
The USB module interfaces to any ULPI-compatible PHY. The primary function of the port controller
block is to isolate the rest of the module from the transceiver, and to move all of the transceiver signaling
into the primary clock domain of the module. This allows the module to run synchronously with the system
processor and its associated resources.
Due to pincount limitations the module only supports certain combinations of PHY interfaces and USB
functionality. Refer to
21.5
This section defines the interface data structures used to communicate control, status, and data between
HCD (software) and the Enhanced Host Controller (hardware). The data structure definitions in this
section support a 32-bit memory buffer address space. The interface consists of a periodic schedule,
periodic frame list, asynchronous schedule, isochronous transaction descriptors, split-transaction
isochronous transfer descriptors, queue heads, and queue element transfer descriptors.
The periodic frame list is the root of all periodic (isochronous and interrupt transfer type) support for the
host controller interface. The asynchronous list is the root for all the bulk and control transfer type support.
Isochronous data streams are managed using isochronous transaction descriptors. Isochronous
Freescale Semiconductor
Host Data Structures
FIFO RAM Controller
PHY Interface
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-36
Table 21-36. Supported PHY Interfaces
for more information.
ULPI
PHY
Host/Device
Function
Universal Serial Bus Interfaces
21-41