MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1542

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23.5.1.6.2
In nap mode all clocks internal to the e500 core are turned off except for its timer facilities clock (the core
time base). The L1 caches do not respond to snoops in nap mode, so if coherency with external I/O
transactions is required, the L1 cache must be flushed before entering nap mode.
Similar to doze mode, interrupts occurring in nap mode cause the device to wake up the e500 core in order
to service the interrupt. However, unless the interrupt service routine changes the control bits that caused
the device to enter nap mode (MSR[WE], and HID0[NAP]), the MPC8536E returns to nap mode after the
interrupt is serviced.
All device logic external to the e500 core remains fully operational in nap mode. Additionally, ASLEEP
and READY pins are both negated.
23.5.1.6.3
In sleep mode, all clocks internal to the e500 core are turned off, including the timer facilities clock.
Several modules clocks of the device logic are also shut down. Only the modules clocks which allows to
wake up the MPC8536E are still running.
The modules which can be used as a wake up source are the Ethernet, USB controllers, GPIO, internal and
external interrupts.
After the core and I/O interfaces have shut down, ASLEEP is asserted and READY is negated.
23.5.1.6.4
In deep sleep mode, all clocks internal to the e500 core are turned off, including the timer facilities clock.
In addition the power supply is removed to the e500 core and the L2 cache.
Several modules’ clocks of the device logic are also shut down. Only those modules’ clocks which allow
to wake up the MPC8536E are still running; modules which can be used as a wake up source are the
Ethernet controllers, USB controllers, GPIO, and internal and external interrupts.
If the separate (asynchronous) PCI_CLK clock signal is used rather than SYSCLK as the PCI clock, then
this clock must be constantly driven, even when in Deep Sleep mode, in order to avoid loss of lock.
For any SerDes that is not disabled through cfg_io_ports[0:2]=001 or cfg_srds2_prtcl[0:2]=111
respectively, the applicable SD_REF_CLK/SD_REF_CLK must be constantly driven, even when in Deep
Sleep mode, in order to avoid loss of lock.
After the core and I/O interfaces have shut down, ASLEEP is asserted, READY is negated and
POWER_EN is negated.
After the device is woken up by one of the wake-up events, the POWER_EN signal is asserted. The power
management controller waits for POWER_OK indication from the regulator in order to make sure the
power level is stable before enabling the the e500 core PLL. In case the POWER_OK is not driven from
an external voltage regulator and is pullup high, the power managment controller will wait for the VRCNT
(voltage ramp-up) timer to expire before enabling the e500 core PLL. The e500 core and the L2 cache are
reset after the device exits from deep sleep mode.
23-50
Nap Mode
Sleep Mode
Deep Sleep Mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor