MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 958

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PRESDIV (bit field) 16-28
PRESDIV (register) 16-8, 16-9, 16-27
Privilege level 3-7, 3-21
Processor version register 3-25
Programmable
Programmable time accumulator (PTA) D-4
Propagation segment time (PROPSEG) 16-27
PROPSEG 16-11, 16-27
PSCK 17-11
PSEG1 16-28
PSEG2 16-9, 16-11, 16-28
PSEGS1 16-11
PSH 13-26, 13-36
PSL 13-36
PT 14-46, 14-52
PTA D-4
PTR, 9-4, 9-37
Pulse-width modulation (PWM) D-36
PVR 3-25
PWM D-36
QACR0 13-35
QACR1 13-36
QACR2 13-38, 13-39
QADC
QADCINT 13-32, 13-33
QADCMCR 13-6, 13-32, 13-33
QADCTEST 13-32, 13-33
QASR 13-40
QASR0 13-41
QASR1 13-42
QCLK 13-21, 13-24
MPC555 / MPC556
USER’S MANUAL
divide
channel service priority 17-4
transfer length 14-14
parameters D-5, D-44, D-46
parameters D-37
features 13-2
pin functions diagram 13-2
registers
frequency 13-25
factor field 16-28
register (PRESDIV) 16-8, 16-27
control register 0 (QACR0) 13-35
control register 1 (QACR1) 13-36
control register 2 (QACR2) 13-39
conversion command word table (CCW) 13-46
interrupt register (QADCINT) 13-32, 13-33
module configuration register (QADCMCR) 13-6,
port
status register (QASR) 13-41, 13-42
test register (QADCTEST) 13-32, 13-33
A data register (PORTQA) 13-33
B data register (PORTQB) 13-33
data direction register (DDRQA) 13-33
QA data direction register (DDRQA) 13-35
QA data register (PORTQA) 13-34
QB data register (PORTQB) 13-34
13-32, 13-33
–Q–
Rev. 15 October 2000
INDEX
QDDR 14-12, 14-41
QILR 14-8
QOM D-6
QPAR 14-11
QPDR 14-10, 14-41
QS 13-42
QSM
QSM Data Direction Register (QDDR) 14-12, 14-41
QSM Interrupt Level Register (QILR) 14-8
QSM Pin Assignment Register (QPAR) 14-11
QSM Port Data Register (QPDR) 14-10, 14-41
QSPI 14-13
QSPI Enable (SPE) 14-41
QSPI Status Register (SPSR) 14-41
Queue 13-14
pin function 14-10
QSPI 14-13
registers
SCI 14-41
block diagram 14-14
enable (SPE) 14-18
finished flag (SPIF) 14-21
initialization operation 14-27
loop mode (LOOPQ) 14-20
master operation flow 14-28
operating modes 14-26
operation 14-24
peripheral chip-selects 14-36
RAM 14-21, 14-22
pointers
operating modes 14-26
operation 14-24
RAM 14-21
pin control registers 14-9
QSPI
SCI
operation 14-50
pins 14-50
registers 14-44
master mode 14-26, 14-33
slave mode 14-26, 14-37
command RAM 14-22
receive RAM 14-22
transmit RAM 14-22
completed queue pointer (CPTQP) 14-24
end queue pointer (ENDQP) 14-24
new queue pointer (NEWQP) 14-24
port QS
control register 0 (SPCR0) 14-16
control register 1 (SPCR1) 14-18
control register 2 (SPCR2) 14-18
control register 3 (SPCR3) 14-19
status register (SPSR) 14-19
control register 0 (SCCR0) 14-45
control register 1 (SCCR1) 14-45
data register (SCDR) 14-49
status register (SCSR) 14-47
wraparound mode 14-37
data direction register (DDRQS) 14-9
data register (PORTQS) 14-10
MOTOROLA
Index-8