MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 159

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
FETCH
DECODE
READ AND EXECUTE
WRITE BACK (TO DEST REG)
L ADDRESS DRIVE
L DATA
LOAD WRITE BACK
BRANCH DECODE
BRANCH EXECUTE
The history buffer maintains the correct architectural machine state. An exception is
taken only when the instruction is ready to be retired from the machine (i.e., after all
previously-issued instructions have already been retired from the machine). When an
exception is taken, all instructions following the excepting instruction are canceled,
i.e., the values of the affected destination registers are restored using the values saved
in the history buffer during the dispatch stage.
Figure 3-4
Table 3-22
fers to the interval from the time an instruction begins execution until it produces a re-
sult that is available for use by a subsequent instruction. Blockage refers to the interval
from the time an instruction begins execution until its execution unit is available for a
subsequent instruction. Note that when the blockage equals the latency, it is not pos-
sible to issue another instruction to the same unit in the same cycle in which the first
instruction is being written back.
2. In the execute stage, each execution unit that has an executable instruction ex-
3. In the writeback stage, the execution unit writes the result to the destination reg-
4. In the retirement stage, the history buffer retires instructions in architectural or-
/
MPC556
ecutes the instruction. (For some instructions, this occurs over multiple cycles.)
ister and reports to the history buffer that the instruction is completed.
der. An instruction retires from the machine if it completes execution with no ex-
ceptions and if all instructions preceding it in the instruction stream have
finished execution with no exceptions. As many as six instructions can be re-
tired in one clock.
shows basic instruction pipeline timing.
indicates the latency and blockage for each type of instruction. Latency re-
Figure 3-4 Basic Instruction Pipeline
I1
CENTRAL PROCESSING UNIT
I1
Rev. 15 October 2000
I1
I2
I1
I1
I1
I2
I1
I3
STORE
I2
LOAD
I1
I2
MOTOROLA
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