MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 313

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
and asserts or negates the BDIP signal. If the master does not intend to drive another
data beat following the current one, it negates BDIP to indicate to the slave that the
next data beat transfer is the last data of the burst write transfer.
BDIP has two basic timings: normal and late (see
late timing mode, assertion of BDIP is delayed by the number of wait states in the first
data beat. This implies that for zero-wait-state cycles, BDIP assertion time is identical
in normal and late modes. Cycles with late BDIP generation can occur only during cy-
cles for which the memory controller generates TA internally. Refer to
MEMORY CONTROLLER
In the MPC555 / MPC556, no internal master initiates write bursts. The MPC555 /
MPC556 is designed to perform this kind of transaction in order to support an external
master that is using the memory controller services. Refer to
External Master
During the data phase of a burst read cycle, the master receives data from the ad-
dressed slave. If the master needs more than one data beat, it asserts BDIP. Upon
receiving the second-to-last data beat, the master negates BDIP. The slave stops driv-
ing new data after it receives the negation of the BDIP signal at the rising edge of the
clock.
/
MPC556
Support.
for more information.
EXTERNAL BUS INTERFACE
Rev. 15 October 2000
Figure 9-13
10.7 Memory Controller
and
Figure
SECTION 10
9-14). In the
MOTOROLA
9-17