MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 238

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.13.4 System Timer Registers
6.13.4.1 Decrementer Register
DEC — Decrementer Register
6.13.4.2 Time Base SPRs
MPC555
USER’S MANUAL
HRESET/SRESET: UNCHANGED
Bit(s)
0
20:25
28:31
MSB
0:17
18
19
26
27
0
The following sections describe registers associated with the system timers. These fa-
cilities are powered by the KAPWR and can preserve their value when the main power
supply is off. Refer to
order to guarantee this data retention.
The 32-bit decrementer register is defined by the MPC555 / MPC556 architecture. The
values stored in this register are used by a down counter to cause decrementer excep-
tions. The decrementer causes an exception whenever bit zero changes from a logic
zero to a logic one. A read of this register always returns the current count value from
the down counter.
Contents of this register can be read or written to by the mfspr or the mtspr instruc-
tion. The decrementer register is reset by PORESET. HRESET and SRESET do not
affect this register. The decrementer is powered by standby power and can continue
to count when standby power is applied.
Refer to
The TB is a 64-bit register containing a 64-bit integer that is incremented periodically.
There is no automatic initialization of the TB; the system software must perform this
0
0
/
0
MPC556
Name
DEXT
IBMT
IEXT
DBM
—
—
—
0
3.9.5 Decrementer Register (DEC)
0
Reserved
Instruction external transfer error acknowledge. This bit is set if the cycle was terminated by an
externally generated TEA signal when an instruction fetch was initiated.
Instruction transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor
time-out when an instruction fetch was initiated.
Reserved
Data external transfer error acknowledge. This bit is set if the cycle was terminated by an exter-
nally generated TEA signal when a data load or store is requested by an internal master.
Data transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor time-
out when a data load or store is requested by an internal master.
Reserved
0
0
0
SYSTEM CONFIGURATION AND PROTECTION
8.3.3 Pre-Divider
0
Table 6-15 TESR Bit Descriptions
0
0
0
Rev. 15 October 2000
Decrementing Counter
0
0
PORESET
0
for details on the required actions needed in
0
0
Description
for more information on this register.
0
0
0
0
0
0
0
0
0
0
MOTOROLA
0
SPR 22
0
0
LSB
6-30
31
0