MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 424

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
13.9.1 Conversion Cycle Times
MPC555
USER’S MANUAL
VSSA
VDDA
PQA7
PQA0
PQB7
PQB0
VRH
VRL
Total conversion time is made up of initial sample time, final sample time, and resolu-
tion time. Initial sample time refers to the time during which the selected input channel
is driven by the buffer amplifier onto the sample capacitor. The buffer amplifier can be
disabled by means of the BYP bit in the CCW. During the final sampling period, ampli-
fier is bypassed, and the multiplexer input charges the RC DAC array directly. During
the resolution period, the voltage in the RC DAC array is converted to a digital value
and stored in the SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16
QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is
ten QCLK cycles.
Sample and resolution require a minimum of 14 QCLK clocks (7 µs with a 2-MHz
QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total
conversion time is 13.0 µs with a 2-MHz QCLK.
Figure 13-5
sampling period of two QCLK cycles.
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
ANALOG
POWER
10 BIT A/D CONVERTER
illustrates the timing for conversions. This diagram assumes a final
10 BIT RC
DAC
Figure 13-4 QADC64 Module Block Diagram
COMPAR-
CHAN. DECODE & MUX
ATOR
SAMPLE
BUFFER
16: 1
INPUT
CSAMP
Rev. 15 October 2000
APPROXIMATION
6
SUCCESSIVE
STATE MACHINE & LOGIC
REGISTER
10
SAR Timing
BIAS CIRCUIT
CHAN.[5:0]
10
POWER
DOWN
2
SAR
CCW
BUF
BUF
10
10
END OF CONV.
END OF SMP
STOP
RST
QCLK
WCCW
CCW
SAR
QADC64 DETAIL BLOCK
MOTOROLA
RSAR
13-12

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