MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 953

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CSG 21-50
CSH 21-50
CTA 21-48
CTB 21-48
CTC 21-48
CTD 21-48
CTE 21-50
CTF 21-50
CTG 21-50
CTH 21-50
CTR 3-5
CWP 13-42
Cyclic redundancy check error (CRCERR) 16-31
D(0
D0 20-3
DAC 13-1
DAE/source instruction service register 3-22
DAR 3-22, 3-46, 3-51, 3-52
DAR, 3-46, 3-51
Data
Data address register 3-22
Data space only 20-3
data storage interrupt, 3-45
DCNR 17-19
DDRQA 13-33, 13-35
DDRQS 14-9, 14-33, 14-37
Debug enable register 21-55
debug mode disable, 3-45
DEC 3-23
DECE 21-54
DECEE 21-56
Decrementer
Delay
DER 21-55
Development Port
Digital
DIO D-38
DIS 20-3
Disable TPU2 pins field (DTPU) 17-20
Disabled mode 13-18
Discrete input/output (DIO) D-38
DIV2 17-20
DIV8 clock 17-7
Divide by two control field (DIV2) 17-20
DIW0EN 21-48
MPC555 / MPC556
USER’S MANUAL
31), 9-6
field for RX/TX frames (TOUCAN) 16-5
frame 14-50
register 3-23
after transfer (DT) 14-23, 14-35
before SCK (DSCKL) 14-18
trap enable selection 21-48
control section
input
to analog converter (DAC) 13-14
contents 13-1, 13-14–13-29
/output port (PQA) 13-3
port (PQB) 13-4
–D–
Rev. 15 October 2000
INDEX
DIW1EN 21-48
DIW2EN 21-48
DIW3EN 21-48
DLW0EN 21-52
DLW1EN 21-52
Double
DPI 21-55
DPTRAM 18-4
DSCK 14-23
DSCKL 14-18
DSCR 17-12
DSISR 3-22, 3-46, 3-51, 3-52
DSSR 17-14
DT 14-23
DTL 14-18
DTPU 17-20
EA 3-33
EBRK 21-55
ECR 21-53
EE bit 3-21, 3-26
Effective address 3-33
EID 3-26
EIE 3-26
eieio, 3-43
ELE bit 3-21
EMPTY 16-5
EMU 17-4, 17-11
Emulation
Encoded
Ending queue pointer (ENDQP) 14-19
End-of-
End-of-queue condition 13-45
ENDQP 14-19, 14-24
Entry
EOF 16-16
EOQ 13-17
EP bit 3-21
ERRINT 16-32
Error
ESTAT 16-30
ETBANK 17-20
ETRIG 13-4
Event timing 17-3
Exception cause register 21-53
Exception prefix 3-21
Exceptions 3-34
-buffered 14-52, 14-56
control (EMU) 17-11
support 17-4
one of three channel priority levels (CH) 17-18
time function for each channel (CHANNEL) 17-16
type of host service (CH) 17-18
frame (EOF) 16-16
table bank select field (ETBANK) 17-20
conditions 14-56
counters 16-9
interrupt (ERRINT) 16-32
classes 3-34
–E–
MOTOROLA
Index-3