MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 240

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TBSCR — Time Base Control and Status Register
6.13.4.5 Real-Time Clock Status and Control Register
MPC555
USER’S MANUAL
RTCSC — Real-Time Clock Status and Control Register
MSB
Bit(s)
10:11
PORESET:
MSB
0
0
0:7
12
13
14
15
0
0
8
9
RESET:
The RTCSC is used to enable the different RTC functions and to report the source of
the interrupts. The register can be read anytime. A status bit is cleared by writing it to
a one. (Writing a zero does not affect a status bit’s value.) More than one status bit can
be cleared at a time. This register is locked after RESET. Unlocking is accomplished
by writing 0x55CCAA33 to its associated key register. See
Registers Lock
1
0
/
1
0
REFAE
REFBE
TBIRQ
MPC556
Name
REFA
REFB
TBF
TBE
—
2
0
2
0
Time base interrupt request. These bits determine the interrupt priority level of the time base. Re-
fer to
Reference A (TBREF0) interrupt status.
0 = No match detected
1 = TBREF0 value matches value in TBL
Reference B (TBREF1) interupt status.
0 = No match detected
1 = TBREF1 value matches value in TBL
Reserved
Reference A (TBREF0) interrupt enable. If this bit is set, the time base generates an interrupt
when the REFA bit is set.
Reference B (TBREF1) interrupt enable. If this bit is set, the time base generates an interrupt
when the REFB bit is set.
Time base freeze. If this bit is set, the time base and decrementer stop while FREEZE is assert-
ed.
Time base enable
0 = Time base and decrementer are disabled
1 = Time base and decrementer are enabled
3
0
3
0
TBIRQ
RTCIRQ
Mechanism.
6.4 Interrupt Controller
SYSTEM CONFIGURATION AND PROTECTION
4
0
4
0
Table 6-16 TBSCR Bit Descriptions
5
0
5
0
Rev. 15 October 2000
6
0
6
0
for interrupt level encodings.
7
0
7
0
REFA REFB
SEC
8
0
8
0
Description
ALR
9
0
9
0
served
RESERVED
10
Re-
0
10
0
11
8.9.3.2 Keep Alive Power
0
4M
11
—
REFAE REFBE
12
SIE
12
0
0
ALE
13
13
0
0
0x2F C200
0x2F C220
MOTOROLA
RTF
14
TBF
0
14
0
RTE
LSB
LSB
TBE
15
—
6-32
15
0