MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 405

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

12.4 Interrupt Operation
MPC555
USER’S MANUAL
Table 12-2
form each type of bus cycle. It is assumed in this table that the IMB3 is available to the
UIMB at all times (fastest possible case).
The interrupts from the modules on the IMB3 are propagated to the interrupt controller
in the USIU through the UIMB interface. The UIMB interrupt synchronizer latches the
Interrupts from the IMB3 and drives them onto the U-bus, where they are latched by
the USIU interrupt controller.
CLKOUT
IMB Clock
CLKOUT
IMB Clock
/
MPC556
Bus Cycle (from U-bus Transfer Start
The UIMB interface dynamically interprets the port size of the ad-
dressed module during each bus cycle, allowing bus transfers to and
from 16-bit and 32-bit IMB modules. During a bus transaction, the
slave module on the IMB signals its port size (16- or 32-bit) via an in-
ternal port size signal.
to U-bus Transfer Acknowledge)
shows the number of system clock cycles that the UIMB requires to per-
Table 12-2 Bus Cycles and System Clock Cycles
Dynamically-sized write
Dynamically-sized read
Figure 12-3 IMB Clock – Half-Speed IMB Bus
Figure 12-2 IMB Clock – Full-Speed IMB Bus
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
Normal write
Normal read
U-BUS TO IMB3 BUS INTERFACE (UIMB)
B4
B4
B1
Rev. 15 October 2000
B2
B1
NOTE
B3
Number of System Clock Cycles
Full Speed
4
4
6
6
B4
B2
B1
6
6
10
10
Half Speed
B2
B3
B3
MOTOROLA
12-3