MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 465

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Access
MPC555
USER’S MANUAL
S/U
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S/U
S/U
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S/U
S/U
S/U
S
T
S
S
1
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0x30 500A
0x30 500C
0x30 500E
0x30 501A
0x30 501C
0x30 501E
0x30 502A
0x30 5000
0x30 5002
0x30 5004
0x30 5006
0x30 5008
0x30 5010
0x30 5012
0x30 5014
0x30 5016
0x30 5018
0x30 5020
0x30 5022
0x30 5024
0x30 5026
0x30 5028
MPC556
Address
MSB
0
QSMCM Pin Assignment Register (PQSPAR)
Dual SCI Interrupt Level (QDSCI_IL)
See
See
2
See
QSPI Control Register 3 (SPCR3)
Reserved
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 14-10
Table 14-17
Table 14-5
Table 14-1 QSMCM Register Map
Reserved
QSMCM Module Configuration Register (QSMCMMCR)
Rev. 15 October 2000
for bit descriptions.
for bit descriptions.
for bit descriptions.
See
See
See
See
See
See
See
See
See
See
QSCI1 Control Register (QSCI1CR)
See
SCI2 Control Register 0 (SCC2R0)
SCI2 Control Register 1 (SCC2R1)
QSCI1 Status Register (QSCI1SR)
SCI1Control Register 0 (SCC1R0)
SCI1Control Register 1 (SCC1R1)
QSPI Control Register 0 (SPCR0)
QSPI Control Register 1 (SPCR1)
QSPI Control Register 2 (SPCR2)
14.6.1 Port QS Data Register (PORTQS)
QSMCM Test Register (QTEST)
SCI1 Status Register (SC1SR)
SCI2 Status Register (SC2SR)
SCI1 Data Register (SC1DR)
SCI2 Data Register (SC2DR)
Table 14-13
Table 14-15
Table 14-16
Table 14-30
Table 14-31
Table 14-23
Table 14-24
Table 14-25
Table 14-26
Table 14-4
QSMCM Port Q Data Register (PORTQS)
Reserved
Reserved
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
QSMCM Data Direction Register (DDRQS)
Queued SPI Interrupt Level (QSPI_IL)
See
See
See
QSPI Status Register (SPSR)
Table 14-11
Table 14-18
Table 14-6
Reserved
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
MOTOROLA
14-3
LSB
15