MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 141

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CTR — Count Register
MSB
3.7.7 Count Register (CTR)
3.8 PowerPC VEA Register Set — Time Base
TB — Time Base (Read Only)
MPC555
USER’S MANUAL
0
32-63
0
0-31
Bits
The count register (CTR) is a 32-bit register for holding a loop count that can be dec-
remented during execution of branch instructions that contain an appropriately coded
BO field. If the value in CTR is 0 before being decremented, it is –1 afterward. The
count register provides the branch target address for the Branch Conditional to Count
Register (bcctrx) instruction.
The PowerPC virtual environment architecture (VEA) defines registers in addition to
those in the UISA register set. The PowerPC VEA register set can be accessed by all
software with either user- or supervisor-level privileges.
The PowerPC VEA includes the time base facility (TB), a 64-bit structure that contains
a 64-bit unsigned integer that is incremented periodically. The frequency at which the
counter is updated is implementation-dependent. For details on the time base clock in
the MPC555 / MPC556, refer to
/ MPC556 Internal Clock
CR).
The TB consists of two 32-bit registers: time base upper (TBU) and time base lower
(TBL). In the context of the VEA, user-level applications are permitted read-only ac-
cess to the TB. The OEA defines supervisor-level access to the TB for writing values
to the TB. Different SPR encodings are provided for reading and writing the time base.
In 32-bit PowerPC implementations such as the RCPU, it is not possible to read the
entire 64-bit time base in a single instruction. The mftb simplified mnemonic copies
the lower half of the time base register (TBL) to a GPR, and the mftbu simplified mne-
monic copies the upper half of the time base (TBU) to a GPR.
1
2
Name
/
TBU
TBL
3
MPC556
4
Time Base (Upper) — The high-order 32 bits of the time base
Time Base (Lower) — The low-order 32 bits of the time base
5
Table 3-11 Time Base Field Definitions (Read Only)
6
7
TBU
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Signals, and
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
6.7 MPC555 / MPC556 Time Base
RESET: UNCHANGED
RESET: UNCHANGED
Loop Count
31 32
8.12.1 System Clock Control Register (SC-
Description
TBL
(TB),
SPR 268, 269
8.6 MPC555
MOTOROLA
SPR 9
3-19
63
LSB
31