MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 610

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

16.7.5 Control Register 1
CANCTRL1 — Control Register 1
MPC555
USER’S MANUAL
MSB
CNRX1
CNRX0
NOTES:
0
0
RESET:
Pin
1. The CNRX1 signal is not available on the MPC555 / MPC556.
1
1
0
/
NOTES:
MPC556
TXMODE[1:0]
RX1
1. Full CMOS drive indicates that both dominant and recessive levels are driven by the chip.
2. The CNTX1 signal is not available on the MPC555 / MPC556.
3. Open drain drive indicates that only a dominant level is driven by the chip. During a reces-
X
X
0
1
sive level, the CNTX0 and CNTX1 pins are disabled (three stated), and the electrical level
is achieved by external pull-up/pull-down devices. The assertion of both Tx mode bits caus-
es the polarity inversion to be cancelled (open drain mode forces the polarity to be positive).
2
0
1X
00
01
RX0
CANCTRL0
X
X
3
0
0
1
Table 16-14 RX MODE[1:0] Configuration
Full CMOS
Full CMOS; negative polarity (CNTX0 = 1, CNTX1
Open drain
A logic zero on the CNRX1 pin is interpreted as a dominant bit; a logic one on the
CNRX1 pin is interpreted as a recessive bit
A logic one on the CNRX1 pin is interpreted as a dominant bit; a logic zero on the
CNRX1 pin is interpreted as a recessive bit
A logic zero on the CNRX0 pin is interpreted as a dominant bit; a logic one on the
CNRX0 pin is interpreted as a recessive bit
A logic one on the CNRX0 pin is interpreted as a dominant bit; a logic zeroon the
CNRX0 pin is interpreted as a recessive bit
Table 16-15 Transmit Pin Configuration
4
0
CAN 2.0B CONTROLLER MODULE
5
0
1
3
; positive polarity (CNTX0 = 0, CNTX1
; positive polarity
Rev. 15 October 2000
6
0
7
0
Transmit Pin Configuration
SAMP
Receive Pin Configuration
8
0
served
Re-
9
0
TSYNC LBUF
10
0
2
2
= 0 is a dominant level)
= 1 is a dominant level)
11
0
0D
12
0
13
0
0x30 7086
0x30 7486
PROPSE
MOTOROLA
2
14
0
16-28
LSB
15
0