MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 730

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.5.6.4 Development Port Serial Communications — Clock Mode Selection
MPC555
USER’S MANUAL
All of the serial transmissions are clock transmissions and are therefore synchronous
communications. However, the transmission clock may be either synchronous or
asynchronous with the system clock (CLKOUT). The development port allows the user
to select two methods for clocking the serial transmissions. The first method allows the
transmission to occur without being externally synchronized with CLKOUT, in this
mode a serial clock DSCK must be supplied to the MPC555 / MPC556. The other com-
munication method requires a data to be externally synchronized with CLKOUT.
The first clock mode is called “asynchronous clock” since the input clock (DSCK) is
asynchronous with CLKOUT. To be sure that data on DSDI is sampled correctly, tran-
sitions on DSDI must occur a setup time ahead and a hold time after the rising edge
of DSCK. This clock mode allows communications with the port from a development
tool which does not have access to the CLKOUT signal or where the CLKOUT signal
has been delayed or skewed. Refer to the timing diagram in
The second clock mode is called “synchronous self clock”. It does not require an input
clock. Instead the port is timed by the system clock. The DSDI input is required to meet
setup and hold time requirements with respect to CLKOUT rising edge. The data rate
for this mode is always the same as the system clock. Refer to the timing diagram in
Figure
The selection of clock or self clock mode is made at reset. The state of the DSDI input
is latched eight clocks after SRESET negates. If it is latched low, asynchronous clock
mode is enabled. If it is latched high then synchronous self clock mode is enabled.
Since DSDI is used to select the development port clocking scheme, it is necessary to
prevent any transitions on DSDI during this time from being recognized as the start of
a serial transmission. The port will not begin scanning for the start bit of a serial trans-
mission until 16 clocks after the negation of SRESET. If DSDI is asserted 16 clocks
after SRESET negation, the port will wait until DSDI is negated to begin scanning for
the start bit.
/
MPC556
21-9.
DEVELOPMENT SUPPORT
Rev. 15 October 2000
Figure 21-8
MOTOROLA
21-34