MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 241

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.13.4.6 Real-Time Clock Register (RTC)
RTC —Real-Time Clock Register
6.13.4.7 Real-Time Clock Alarm Register (RTCAL)
RTCAL — Real-Time Clock Alarm Register
MPC555
USER’S MANUAL
Bit(s)
MSB
MSB
0:7
10
11
12
13
14
15
0
0
8
9
The real-time clock register is a 32-bit read write register. It contains the current value
of the real-time clock. A write to the RTC resets the seconds timer to zero. This register
is locked after RESET. Unlocking is accomplished by writing 0x55CCAA33 to its as-
sociated key register. See
The RTCAL is a 32-bit read/write register. When the value of the RTC is equal to the
value programmed in the alarm register, a maskable interrupt is generated.
The alarm interrupt will be generated as soon as there is a match between the ALARM
field and the corresponding bits in the RTC. The resolution of the alarm is 1 sec. This
register is locked after RESET. Unlocking is accomplished by writing 0x55CCAA33 to
its associated key register. See
nism.
/
RTCIRQ
MPC556
Name
SEC
ALR
ALE
RTF
RTE
SIE
4M
—
Real-time clock interrupt request. Thee bits determine the interrupt priority level of the RTC. Re-
fer to
Once per second interrupt. This status bit is set every second. It should be cleared by the soft-
ware.
Alarm interrupt. This status bit is set when the value of the RTC equals the value programmed in
the alarm register.
Reserved
Real-time clock source
0 = RTC assumes that it is driven by 20 MHz to generate the seconds pulse.
1 = RTC assumes that it is driven by 4 MHz
Second interrupt enable. If this bit is set, the RTC generates an interrupt when the SEC bit is set.
Alarm interrupt enable. If this bit is set, the RTC generates an interrupt when the ALR bit is set.
Real-time clock freeze. If this bit is set, the RTC stops while FREEZE is asserted.
Real-time clock enable
0 = RTC is disabled
1 = RTC is enabled
6.4 Interrupt Controller
SYSTEM CONFIGURATION AND PROTECTION
Table 6-17 RTCSC Bit Descriptions
8.9.3.2 Keep Alive Power Registers Lock
Rev. 15 October 2000
8.9.3.2 Keep Alive Power Registers Lock Mecha-
RESET: UNCHANGED
RESET: UNCHANGED
for interrupt level encodings.
ALARM
RTC
Description
Mechanism.
0x2F C22C
0x2F C224
MOTOROLA
LSB
LSB
6-33
31
31