MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 470

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
14.5.6 QSMCM Test Register (QTEST)
14.5.7 QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL)
QDSCI_IL — QSM2 Dual SCI Interrupt Level Register
MPC555
USER’S MANUAL
RESET:
MSB
Bit(s)
12:15
Bit(s)
9:11
0
0
8:15
The QTEST register is used for factory testing of the MCU.
The QDSCI_ILI and QSPI_IL registers determine the interrupt level requested by the
QSMCM. The two SCI submodules (DSCI) share a 5-bit interrupt level field, ILDSCI.
The QSPI uses a separate field, ILQSPI. The level value is used to determine which
interrupt is serviced first when two or more modules or external peripherals simulta-
neously request an interrupt. The user can select among 32 levels. This register can
be accessed only when the CPU is in supervisor mode.
2:7
0:2
3:7
0
1
8
Reserved
/
MPC556
1
0
ILDSCI
Name
STOP
SUPV
Name
FRZ1
IARB
2
0
3
0
Stop enable. Refer to
0 = Normal clock operation
1 = Internal clocks stopped
Freeze1 bit. Refer to
0 = Ignore the FREEZE signal
1 = Halt the QSMCM (on transfer boundary)
Reserved
Supervisor /Unrestricted. Refer to
0 = Assigned registers are unrestricted (user access allowed)
1 = Assigned registers are restricted (only supervisor access allowed)
Reserved
This field currently has no effect. It is implemented for future interrupt arbitration
schemes.
Reserved
Interrupt level of SCIs
00000 = lowest interrupt level request (level 0)
11111 = highest interrupt level request (level 31)
Reserved
Table 14-4 QSMCMMCR Bit Descriptions
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 14-5 QDSCI_IL Bit Descriptions
4
0
ILDSCI
5
0
Rev. 15 October 2000
6
0
14.5.2 Freeze
14.5.1 Low-Power Stop
7
0
14.5.3 Access
8
Operation.
Description
Description
9
Operation.
10
Protection.
RESERVED
11
12
13
0x30 5004
MOTOROLA
14
LSB
14-8
15

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