MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 272

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.6.2 CLKOUT
8.6.3 Engineering Clock
MPC555
USER’S MANUAL
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
CLKOUT has the same frequency as the general system clock (GCLK2_50). Unlike
the main system clock GCLK1/GCLK2 however, CLKOUT (and GCLK2_50) repre-
sents the external bus clock, and thus will be one-half of the main system clock if the
external bus is running at half speed (EBDF = 0b01). The CLKOUT frequency defaults
to VCO/2. CLKOUT can drive full- or half-strength or be disabled. The drive strength
is controlled in the system clock and reset-control register (SCCR). Disabling or de-
creasing the strength of CLKOUT can reduce power consumption, noise, and electro-
magnetic interference on the printed circuit board.
When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low
state (provided that BUCS = 0).
ENGCLK is an output clock with a 50% duty cycle. Its frequency defaults to VCO/128
which is one-sixtyfourth of the main system frequency. ENGCLK frequency can be pro-
grammed to the main system frequency divided by a factor from one to 64, as con-
trolled by the ENGDIV[0:5] bits in the SCCR. ENGCLK can drive full- or half-strength
or be disabled (remaining in the high state). The drive strength is controlled by the EE-
CLK[0:1] bits in the SCCR. Disabling ENGCLK can reduce power consumption, noise,
and electromagnetic interference on the printed circuit board.
1.
Mask sets prior to K62N default to VCO/4.
/
MPC556
Figure 8-7 Clocks Timing For DFNH = 1 (or DFNL = 0)
CLOCKS AND POWER CONTROL
Rev. 15 October 2000
MOTOROLA
8-12
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