MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 441

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

13.10.5 Periodic/Interval Timer
13.11 Interrupts
MPC555
USER’S MANUAL
cycles of the IMB clock. It also shows that when PSL = 7, the QCLK remains low for
eight IMB clock cycles.
The on-chip periodic/interval timer is enabled to generate trigger events at a program-
mable interval, initiating execution of queue 1 and/or 2. The periodic/interval timer
stays reset under the following conditions:
Two other conditions which cause a pulsed reset of the timer are:
During the low power stop mode, the periodic/interval timer is held in reset. Since low
power stop mode causes QACR1 and QACR2 to be reset to zero, a valid periodic or
interval timer mode must be written after stop mode is exited to release the timer from
reset.
When the IMB internal FREEZE line is asserted and a periodic or interval timer mode
is selected, the timer counter is reset after the conversion in-progress completes.
When the periodic or interval timer mode has been enabled (the timer is counting), but
a trigger event has not been issued, the freeze mode takes effect immediately, and the
timer is held in reset. When the internal FREEZE line is negated, the timer counter
starts counting from the beginning.
The QADC64 supports both polled and interrupt driven operation. Status bits in QASR
reflect the operating condition of each queue and can optionally generate interrupts
when enabled by the appropriate bits in QACR1 and/or QACR2.
Figure 13-10
• Queue 1 and queue 2 are programmed to any queue operating mode which does
• Interval timer single-scan mode is selected, but the single-scan enable bit is set
• IMB system reset or the master reset is asserted
• Stop mode is selected
• Freeze mode is selected
• Roll-over of the timer counter
• A queue operating mode change from one periodic/interval timer mode to another
/
not use the periodic/interval timer
to zero
periodic/interval timer mode, depending on which queues are active in timer
mode.
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
The periodic/interval timer will not reset for a queue 2 operating mode
change from one periodic/interval timer mode to another periodic/in-
terval timer mode while queue 1 is in an active periodic/interval timer
mode.
displays the QADC64 interrupt flow.
Rev. 15 October 2000
NOTE
MOTOROLA
13-29