MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 161

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.13.4 Exceptions
3.13.5 The Branch Processor
3.13.6 Instruction Fetching
3.13.7 Branch Instructions
3.13.7.1 Invalid Branch Instruction Forms
3.13.7.2 Branch Prediction
3.13.8 The Fixed-Point Processor
3.13.8.1 Fixed-Point Instructions
MPC555
USER’S MANUAL
tation-dependent software emulation interrupt. Invalid and preferred instruction forms
treatment by the MPC555 / MPC556 is described under the specific processor compli-
ance sections.
Invocation of the system software for any instruction-caused exception in the MPC555
/ MPC556 is precise, regardless of the type and setting.
The core fetches a number of instructions into its internal buffer (the instruction pre-
fetch queue) prior to execution. If a program modifies the instructions it intends to ex-
ecute, it should call a system library program to ensure that the modifications have
been made visible to the instruction fetching mechanism prior to execution of the mod-
ified instructions.
The core implements all the instructions defined for the branch processor by the UISA
in the hardware. For performance of various instructions, refer to
manual.
Bits marked with z in the BO encoding definition are discarded by the MPC555 /
MPC556 decoding. Thus, these types of invalid form instructions yield result of the de-
fined instructions with the z bit zero. If the decrement and test CTR option is specified
for the bcctr or bcctrl instructions, the target address of the branch is the new value
of the CTR. Condition is evaluated correctly, including the value of the counter after
decrement.
The core uses the y bit to predict path for pre-fetch. Prediction is only done for not-
ready branch conditions. No prediction is done for branches to link or count register if
the target address is not ready. Refer to RCPU Reference Manual (Conditional Branch
Control) for more information.
The core implements the following instructions:
• Fixed-point arithmetic instructions
• Fixed-point compare instructions
• Fixed-point trap instructions
• Fixed-point logical instructions
/
MPC556
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
Table 3-22
MOTOROLA
of this
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