MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 407

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
Table 12-4
multiplexing. In this case the ILBS lines remain at 00 at all times, as shown in
12-4. In this mode, no interrupts from IMB modules which assert on levels 8 through
31 are ever latched by the Interrupt synchronizer. Time multiplexing is disabled during
reset, but the reset default value enables time multiplexing as soon as reset is re-
leased if the reset default value is not 00.
The timing for the scheme and the values of ILBS and the interrupt levels driven onto
the IMB IRQ lines are shown in
of four clocks and an average latency of two clocks before the interrupt request can
reach the interrupt synchronizer.
The IRQMUX bits determine how many levels of IMB interrupts are sampled. Refer to
Table
IRQMUX[0:1]
ILBS [0:1]
IMB CLOCK
IMB LVL[0:7]]
/
00
01
10
11
MPC556
12-4.
shows ILBS sequencing. Programming IRQMUX[0:1] to 00 disables time
Figure 12-5 Time-Multiplexing Protocol for IRQ pins
00, 00, 00.....
00, 01, 00, 01....
00, 01, 10, 00, 01, 10,.....
00, 01, 10, 11, 00, 01, 10, 11,....
ILBS[0:1]
00
01
10
11
00
Table 12-3 ILBS Signal functionality
U-BUS TO IMB3 BUS INTERFACE (UIMB)
Table 12-4 IRQMUX Functionality
ILBS sequence
IMB interrupt sources mapped onto 0:7 levels will
drive interrupts onto IMB IRQ[0:7]
IMB interrupt sources mapped onto 8:15 levels will
drive interrupts onto IMB IRQ[0:7]
IMB interrupt sources mapped onto 16:23 levels will
drive interrupts onto IMB IRQ[0:7]
IMB interrupt sources mapped onto 24:31 levels will
drive interrupts onto IMB IRQ[0:7]
01
LVL
0:7
Rev. 15 October 2000
Figure
10
LVL
8:15
12-5. This scheme causes a maximum latency
.
11
16:23
LVL
Description
Latch 0:7 IMB interrupt levels
Latch 0:15 IMB interrupt levels
Latch 0:23 IMB interrupt levels
Latch 0:31 IMB interrupt levels
24:31
00
LVL
01
LVL
0:7
Description
10
11
MOTOROLA
Table
12-5