MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 203

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
5.1 Module Overview
MPC555 / MPC556
USER’S MANUAL
The unified system interface unit (USIU) of the MPC555 / MPC556 controls system
start-up, system initialization and operation, system protection, and the external sys-
tem bus. The MPC555 / MPC556 USIU functions include the following:
The system configuration and protection function controls the overall system configu-
ration and provides various monitors and timers, including the bus monitor, software
watchdog timer, periodic interrupt timer, PowerPC decrementer, time base, and real
time clock. The interrupt controller and USIU are also included in the system configu-
ration and protection function. Refer to
PROTECTION
The reset controller receives input from a number of reset sources and takes appro-
priate actions, depending on the source. The reset status register (RSR) reflects the
most recent source to cause a reset. Refer to
The clock synthesizer generates the clock signals used by the SIU as well as the other
modules and external devices. This circuitry can generate the system clock from a 4-
MHz or 20-MHz crystal.
The SIU supports various low-power modes. Each supplies a different range of power
consumption, functionality and wake-up time. Clock generation and low-power modes
are described in
The external bus interface (EBI) handles the transfer of information between the inter-
nal busses and the memory or peripherals in the external address space. The
MPC555 / MPC556 is designed to allow external bus masters to request and obtain
mastership of the system bus, and if required access the on-chip memory and regis-
ters.
The memory controller module provides a glueless interface to many types of memory
devices and peripherals. It supports up to four memory banks, each with its own device
• System configuration and protection
• Interrupt controller
• System reset monitoring and generation
• Clock synthesizer
• Power management
• External bus interface (EBI) control
• Memory controller
• Debug support
SECTION 9 EXTERNAL BUS INTERFACE
for details.
SECTION 8 CLOCKS AND POWER
UNIFIED SYSTEM INTERFACE UNIT
UNIFIED SYSTEM INTERFACE UNIT
Rev. 15 October 2000
SECTION 5
SECTION 6 SYSTEM CONFIGURATION AND
SECTION 7 RESET
describes the bus operation.
CONTROL.
for details.
MOTOROLA
5-1

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