MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 270

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
VCO/2 (e.g., 40 MHz)
2 = 20 MHz (assuming a 20-MHz system frequency) with default power-on reset MF
values.
The general system clock frequency can be switched between different values. The
highest operational frequency can be achieved when the system clock frequency is
determined by DFNH (CSRC bit in the PLPRCR is cleared) and DFNH = 0 (division by
one). The general system clock can be operated at a low frequency (gear mode) or a
high frequency. The DFNL bits in SCCR define the low frequency. The DFNH bits in
SCCR define the high frequency.
The frequency of the general system clock can be changed dynamically with the sys-
tem clock control register (SCCR), as shown in
The frequency of the general system clock can be changed “on the fly” by software.
The user may simply cause the general system clock to switch to its low frequency.
However, in some applications, there is a need for a high frequency during certain pe-
riods. Interrupt routines, for example, may require more performance than the low fre-
quency operation provides, but must consume less power than in maximum frequency
operation. The MPC555 / MPC556 provides a method to automatically switch between
low and high frequency operation whenever one of the following conditions exists:
When neither of these conditions exists and the CSRC bit in PLPRCR is set, the gen-
eral system clock switches automatically back to the low frequency.
Abrupt changes in the divide ratio can cause linear changes in the operating currents
of the MPC555 / MPC556. Insure that the proper power supply filtering is available to
handle this change instantaneously.
When the general system clock is divided, its duty cycle is changed. One phase re-
mains the same (e.g., 12.5 ns @ 40 MHZ) while the other become longer. Note that
CLKOUT does not have a 50% duty cycle when the general system clock is divided.
The CLKOUT waveform is the same as that of GCLK2_50.
• There is a pending interrupt from the interrupt controller. This option is maskable
• The (POW) bit in the MSR is clear in normal operation. This option is maskable
O
/
by the PRQEN bit in the SCCR.
by the PRQEN bit in the SCCR.
MPC556
Figure 8-5 General System Clocks Select
DFNH Divider
DFNL Divider
CLOCKS AND POWER CONTROL
Rev. 15 October 2000
DFNH
DFNL
Figure
8-5.
O
O
Normal
Low Power
O
General System Clock
MOTOROLA
8-10