MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 466

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Access
14.5 QSMCM Global Registers
MPC555
USER’S MANUAL
NOTES:
S/U
S/U
S/U
S/U
S/U
S/U
1. S = Supervisor access only
2. 8-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-bit
3. Note that QRAM offsets have been changed from the original (modular family) QSMCM.
The supervisor-only data space segment contains the QSMCM global registers.
These registers define parameters needed by the QSMCM to integrate with the MCU.
Access to these registers is permitted only when the CPU is operating in supervisor
mode.
Assignable data space can be either restricted to supervisor-only access or unrestrict-
ed to both supervisor and user accesses. The supervisor (SUPV) bit in the QSMCM
module configuration register (QSMCMMCR) designates the assignable data space
as either supervisor or unrestricted. If SUPV is set, then the space is designated as
supervisor-only space. Access is then permitted only when the CPU is operating in su-
pervisor mode. If SUPV is clear, both user and supervisor accesses are permitted. To
clear SUPV, the CPU must be in supervisor mode.
The QSMCM assignable data space segment contains the control and status registers
for the QSPI and SCI submodules, as well as the QSPI RAM. All registers and RAM
can be accessed on byte (8-bits), half-word (16-bits), and word (32-bit) boundaries.
Word accesses require two consecutive IMB3 bus cycles.
The QSMCM global registers contain system parameters used by the QSPI and SCI
submodules for interfacing to the CPU and the intermodule bus. The global registers
are listed in
S/U = Supervisor access only or unrestricted user access (assignable data space).
boundaries.
1
/
0x30 502C –
0x30 504C –
0x30 506C –
0x30 51C0 –
0x30 5140 –
0x30 5180 –
0x30 513F
0x30 51DF
0x30 504A
0x30 506A
0x30 517F
0x30 51BF
MPC556
Address
Table 14-2 QSMCM Global Registers
3
MSB
0
Table 14-1 QSMCM Register Map (Continued)
2
QUEUED SERIAL MULTI-CHANNEL MODULE
Rev. 15 October 2000
Transmit Queue Locations (SCTQ)
Receive Queue Locations (SCRQ)
Transmit Data RAM (TRAN.RAM)
Receive Data RAM (REC.RAM)
Command RAM (COMD.RAM)
Reserved
MOTOROLA
14-4
LSB
15