MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 162

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.13.9 Floating-Point Processor
3.13.9.1 General
3.13.9.2 Optional instructions
3.13.10 Load/Store Processor
MPC555
USER’S MANUAL
All instructions are defined for the fixed-point processor in the UISA in the hardware.
For performance of the various instructions, refer to
The MPC555 / MPC556 implements all floating-point features as defined in the UISA,
including the non-IEEE working mode. Some features require software assistance.
For more information refer to RCPU Reference Manual (Floating-point Load Instruc-
tions) for more information.
The only optional instruction implemented by MPC555 / MPC556 hardware is store
floating point as integer word indexed (stfiwx). An attempt to execute any other op-
tional instruction causes the implementation dependent software emulation interrupt
to be taken.
The load/store processor supports all of the 32-bit implementation fixed-point Power-
PC load/store instructions in the hardware.
• Fixed-point rotate and shift instructions
• Move to/from system register instructions
/
— Move To/From System Register Instructions. Move to/from invalid special
— Fixed-Point Arithmetic Instructions. If an attempt is made to perform any of
MPC556
registers in which spr0 = 1 yields invocation of the privilege instruction error in-
terrupt handler if the processor is in problem state. For a list of all implemented
special registers, refer to
Development Support
the divisions in the divw[o][.] instruction:
0x80000000
<anything>
Then, the contents of RT are 0x80000000 and if Rc =1, the contents of bits in
CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is set to the correct value. If an
attempt is made to perform any of the divisions in the divw[o][.] instruction,
<anything>
contents of bits in CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is set to the
correct value. In cmpi, cmp, cmpli, and cmpl instructions, the L-bit is applicable
for 64-bit implementations. In 32-bit implementations, if L = 1 the instruction
form is invalid. The core ignores this bit and therefore, the behavior when L =
1 is identical to the valid form instruction with L = 0
÷
÷
÷
0
0. Then, the contents of RT are 0x80000000 and if Rc = 1, the
-1
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
SPRs.
Table 3-2 Supervisor-Level
Table
3-22.
SPRs, and
MOTOROLA
Table 3-3
3-40