MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 932

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
MPC555 / MPC556
USER’S MANUAL
Name
NOTES:
115
116
117
118
119
120
121
1. All AC timing is tested to the 5-V levels outlined in
2. TC is defined to be the clock period of f
3. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
Data Hold Time (Inputs)
Master
Slave
Slave Access Time
Slave MISO Disable Time
Data Valid (After SCK Edge)
Master
Slave
Data Hold Time (Outputs)
Master
Slave
Rise Time
Input
Output
up to 50 pF Load, SLRC Bit of PDMCR = “0”
up to 200 pF Load, SLRC Bit of PDMCR = “0”
up to 50 pF, SLRC Bit of PDMCR = “1”
Fall Time
Input
Output
up to 50 pF Load, SLRC Bit of PDMCR = “0”
up to 200 pF Load, SLRC Bit of PDMCR = “0”
up to 50 pF, SLRC Bit of PDMCR = “1”
(T
Table G-17 QSPI Timing (Continued)
A
Function
= T
L
ELECTRICAL CHARACTERISTICS
to T
H
, 50 pF load on all QSPI pins except as noted)
Rev. 15 October 2000
SYS
(IMB Clock).
Table
Symbol
G-4.
t
t
t
t
t
t
dis
t
t
t
ho
ro
fo
hi
a
v
ri
fi
Min
20
10
20
10
20
0
0
0
2
2
2*TC
Max
100
100
TC
50
50
50
25
50
25
1
1
MOTOROLA
Unit
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
ns
ns
ns
G-54

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