MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 343

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.5.10.2 Termination Signals Protocol Summary
9.5.11 Bus Operation in External Master Modes
MPC555
USER’S MANUAL
causes a transfer error acknowledge. See
Size.
Table 9-9
provided by the slave device that is addressed by the initiated transfer.
When an external master takes ownership of the external bus and the MPC555 /
MPC556 is programmed for external master mode operation, the external master can
access the internal space of the MPC555 / MPC556 (see
Modes). In an external master mode, the external master owns the bus, and the direc-
tion of most of the bus signals is inverted, relative to its direction when the MPC555 /
MPC556 owns the bus.
The external master gets ownership of the bus and asserts TS in order to initiate an
external master access. The access is directed to the internal bus only if the input ad-
dress matches the internal address space. The access is terminated with one of the
followings outputs: TA, TEA, or RETRY. If the access completes successfully, the
MPC555 / MPC556 asserts TA, and the external master can proceed with another ex-
ternal master access or relinquish the bus. If an address or data error is detected in-
ternally, the MPC555 / MPC556 asserts TEA for one clock. TEA should be negated
before the second rising edge after it is sampled asserted in order to avoid the detec-
tion of an error for the next bus cycle initiated. TEA is an open drain pin, and the ne-
gation timing depends on the attached pullup. The MPC555 / MPC556 asserts the
RETRY signal for one clock in order to retry the external master access.
If the address of the external access does not match the internal memory space, the
internal memory controller can provide the chip-select and control signals for accesses
that belong to one of the memory controller regions. This feature is explained in
TION 10 MEMORY
Figure 9-34
accesses.
Asserted
Negated
Negated
TEA
/
MPC556
summarizes how the MPC555 / MPC556 recognizes the termination signals
and
Figure 9-35
Asserted
Negated
TA
Table 9-9 Termination Signals Protocol
X
CONTROLLER.
EXTERNAL BUS INTERFACE
illustrate the basic flow of read and write external master
Rev. 15 October 2000
Asserted
RETRY
X
X
9.5.2.3 Single Beat Flow with Small Port
Normal transfer termination
Transfer error termination
Retry transfer termination
Action
6.2 External Master
MOTOROLA
SEC-
9-47