MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 711

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.3.1.4 Context Dependent Filter
21.3.1.5 Ignore First Match
MPC555
USER’S MANUAL
The CPU can be programmed to either recognize internal breakpoints only when the
recoverable interrupt bit in the MSR is set (masked mode) or it can be programmed to
always recognize internal breakpoints (non-masked mode).
When the CPU is programmed to recognize internal breakpoints only when MSRRI =
1, it is possible to debug all parts of the code except when the machine status save/
restore registers (SRR0 and SRR1), DAR (data address register) and DSISR (data
storage interrupt status register) are busy and, therefore, MSRRI = 0, (in the prologues
and epilogues of interrupt/exception handlers).
When the CPU is programmed always to recognize internal breakpoints, it is possible
to debug all parts of the code. However, if an internal breakpoint is recognized when
MSRRI = 0 (SRR0 and SRR1 are busy), the machine enters into a non-restartable
state. For more information refer to
When working in the masked mode, all internal breakpoints detected when MSRRI =
0 are lost. Watchpoints detected in this case are not counted by the debug counters.
Watchpoints detected are always reported on the external pins, regardless of the value
of the MSRRI bit.
Out of reset, the CPU is in masked mode. Programming the CPU to be in non-masked
mode is done by setting the BRKNOMSK bit in the LCTRL2 register. Refer to
L-Bus Support Control Register 2
points (I-breakpoints and L-breakpoints).
In order to facilitate the debugger utilities “continue” and “go from x”, the ignore first
match option is supported for instruction breakpoints. When an instruction breakpoint
is first enabled (as a result of the first write to the instruction support control register or
as a result of the assertion of the MSRRI bit when operating in the masked mode), the
first instruction will not cause an instruction breakpoint if the ignore first match (IFM)
bit in the instruction support control register (ICTRL) is set (used for “continue”).
/
MPC556
Figure 21-2 Partially Supported Watchpoint/Breakpoint Example
Possible false detect on these half-words when using word/multiple
0x00000000
0x00000004
0x00000008
0x0000000C
0x00000010
DEVELOPMENT SUPPORT
Rev. 15 October 2000
3.15.4 Interrupts
The BRKNOMSK bit controls all internal break-
MOTOROLA
21.7.8
21-15