MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 937

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

G.21 MIOS Timing Characteristics
MPC555 / MPC556
USER’S MANUAL
MCPSM Enable to vs_pclk Pulse
NOTES:
Note 1: f
Note 2: The numbers associated with the f
Note 3: vs_pclk is the MIOS prescaler clock which is distributed around the MIOS to counter modules such as the
1. The MCPSM clock prescaler value (MCPSMSCR_PSL[3:0]) should be written to the MCPSMSCR (MCPSM sta-
2. After reset MCPSMSCR_PSL[3:0] is set to 0b0000.
Prescaler enable
All MIOS output pins are slew rate controlled. Slew rate control circuitry adds 90 ns as
minimum to the output timing and 650 ns as a maximum. This slew rate is from 10%
V
tus/control register) before rewriting the MCPSMSCR to set the enable bit (MCPSMSCR_PREN). If this is not
done the prescaler will start with the old value in the MCPSMSCR_PSL[3:0] before reloading the new value into
the counter.
vs_pclk is the MIOS prescaler clock which is distributed to all the counter (e.g., MPWMSM and MMCSM) submod-
ules.
DDH
MIOB vs_pclk
MMCSM and MPWMSM.
SYS
bit (PREN)
to 90% V
Characteristic
is the internal system clock for the IMB3 bus.
Figure G-34 MCPSM Enable to vs_pclk Pulse Timing Diagram
f
SYS
DDH
, an additional 100 ns should be added for total 0 to V
Table G-21 MCPSM Timing Characteristics
1
ELECTRICAL CHARACTERISTICS
SYS
Rev. 15 October 2000
Symbol
t
CPSMC
t
ticks refer to the IMB3 internal state.
CPSMC
(MCPSMSCR_PSL[3:0]) -1
Delay
2
DDH
MOTOROLA
slew rate.
IMB Clock
Cycles
Unit
G-59