MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 487

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.7.4.1 Enabling, Disabling, and Halting the SPI
MPC555
USER’S MANUAL
NEWQP value is changed. After each command is executed, ENDQP and CPTQP are
compared. When a match occurs, the SPIF flag is set and the QSPI stops and clears
SPE, unless wraparound mode is enabled.
At reset, NEWQP is initialized to 0x0. When the QSPI is enabled, execution begins at
queue address 0x0 unless another value has been written into NEWQP. ENDQP is ini-
tialized to 0x0 at reset but should be changed to the last queue entry before the QSPI
is enabled. NEWQP and ENDQP can be written at any time. When NEWQP changes,
the internal pointer value also changes. However, if NEWQP is written while a transfer
is in progress, the transfer is completed normally. Leaving NEWQP and ENDQP set
to 0x0 transfers only the data in transmit RAM location 0x0.
The SPE bit in the SPCR1 enables or disables the QSPI submodule. Setting SPE
causes the QSPI to begin operation. If the QSPI is a master, setting SPE causes the
QSPI to begin initiating serial transfers. If the QSPI is a slave, the QSPI begins moni-
toring the PCS[0]/SS pin to respond to the external initialization of a serial transfer.
When the QSPI is disabled, the CPU may use the QSPI RAM. When the QSPI is en-
abled, both the QSPI and the CPU have access to the QSPI RAM. The CPU has both
read and write access to all 160 bytes of the QSPI RAM. The QSPI can read-only the
transmit data segment and the command control segment and can write-only the re-
ceive data segment of the QSPI RAM.
The QSPI turns itself off automatically when it is finished by clearing SPE. An error
condition called mode fault (MODF) also clears SPE. This error occurs when PCS[0]/
SS is configured for input, the QSPI is a system master (MSTR = 1), and PCS[0]/SS
is driven low externally.
Setting the HALT bit in SPCR3 stops the QSPI on a queue boundary. The QSPI halts
in a known state from which it can later be restarted. When HALT is set, the QSPI fin-
ishes executing the current serial transfer (up to 16 bits) and then halts. While halted,
if the command control bit (CONT of the QSPI RAM) for the last command was assert-
ed, the QSPI continues driving the peripheral chip select pins with the value designat-
ed by the last command before the halt. If CONT was cleared, the QSPI drives the
peripheral chip-select pins to the value in register PORTQS.
If HALT is set during the last command in the queue, the QSPI completes the last com-
mand, sets both HALTA and SPIF, and clears SPE. If the last queue command has
not been executed, asserting HALT does not set SPIF or clear SPE. QSPI execution
continues when the CPU clears HALT.
To stop the QSPI, assert the HALT bit in SPCR3, then wait until the HALTA bit in SPSR
is set. SPE can then be safely cleared, providing an orderly method of shutting down
the QSPI quickly after the current serial transfer is completed. The CPU can disable
the QSPI immediately by clearing SPE. However, loss of data from a current serial
transfer may result and confuse an external SPI device.
/
MPC556
QUEUED SERIAL MULTI-CHANNEL MODULE
Rev. 15 October 2000
MOTOROLA
14-25