MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 358

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.3 Chip-Select Timing
MPC555
USER’S MANUAL
Access speed
Intercycle space time
Synchronous or
asynchronous device
Wait states
If the memory controller is used to support an external master accessing an external
device with bursts, the BDIP input pin is used to indicate to the memory controller
when the burst is terminated.
For addition details, refer to
The GPCM allows a glueless and flexible interface between the MPC555 / MPC556
and SRAM, EPROM, EEPROM, ROM devices and external peripherals. When an ad-
dress and address type matches the values programmed in the BR and OR for one of
the memory controller banks, the attributes for the memory cycle are taken from the
OR and BR registers as well. These attributes include the following fields: CSNT, ACS,
SCY, BSCY, WP, TRLX, BI, PS, and SETA.
Byte write and read-enable signals (WE/BE[0:3]) are available for each byte that is
written to or read from memory. An output enable (OE) signal is provided to eliminate
external glue logic for read cycles. Upon system reset, a global (boot) chip select is
available. This provides a boot ROM chip select before the system is fully configured.
Table 10-1
Note that when a bank is configured for TA to be generated externally (SETA bit is set)
and the TRLX is set, the memory controller requires the external device to provide at
least one wait state before asserting TA to complete the transfer. In this case, the min-
imum transfer time is three clock cycles.
The internal TA generation mode is enabled if the SETA bit in the OR register is ne-
gated. However, if the TA pin is asserted externally at least two clock cycles before the
Timing Attribute
/
MPC556
summarizes the chip-select timing options.
TRLX
EHTR
ACS, CSNT
SCY, BSCY,
SETA, TRLX
Bits/Fields
Table 10-1 Timing Attributes Summary
9.5.3 Burst
MEMORY CONTROLLER
Rev. 15 October 2000
The TRLX (timing relaxed) bit determines strobe timing to be fast or re-
laxed.
The EHTR (extended hold time on read accesses) bit is provided for de-
vices that have long disconnect times from the data bus on read access-
es. EHTR specifies whether the next cycle is delayed one clock cycle
following a read cycle, to avoid data bus contentions. EHTR applies to
all cycles following a read cycle except for another read cycle to the
same region.
The ACS (address-to-chip-select setup) and CSNT (chip-select nega-
tion time) bits cause the timing of the strobes to be the same as the ad-
dress bus timing, or cause the strobes to have setup and hold times
relative to the address bus.
From zero to 15 wait states can be programmed for any cycle that the
memory controller generates. The transfer is then terminated internally.
In simplest case, the cycle length equals (2 + SCY) clock cycles, where
SCY represents the programmed number of wait states (cycle length in
clocks). The number of wait states is doubled if the TRLX bit is set.
When the SETA (external transfer acknowledge) bit is set, TA must be
generated externally, so that external hardware determines the number
of wait states.
Transfer.
Description
MOTOROLA
10-6