MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 292

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PLPRCR — PLL, Low-Power, and Reset-Control Register
SPLS
U = Unaffected by reset
MPC555
USER’S MANUAL
MSB
16
S
U
0
Bit(s)
0:11
U
0
12
13
14
POWER-ON RESET:
POWER-ON RESET:
TEXP
HARD RESET:
HARD RESET:
17
S
1
1
U
1
/
MPC556
LOCSS
SERVE
Name
LOCS
RE-
MF
18
—
D
U
0
U
2
TMIST
19
U
3
0
0
Multiplication factor bits. The output of the VCO is divided to generate the feedback signal to
the phase comparator. The MF bits control the value of the divider in the SPLL feedback
loop. The phase comparator determines the phase shift between the feedback signal and
the reference clock. This difference results in either an increase or decrease in the VCO out-
put frequency.
The MF bits can be read and written at any time. However, this field can be write-protected
by setting the MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the MF bits caus-
es the SPLL to lose lock. Also, the MF field should not be modified when entering or exiting
from low power mode (LPM change), or when back-up clock is active.
The normal reset value for the DFNH bits is zero (divide by one). When the PLL is operating
in one-to-one mode, the multiplication factor is set to x1 (MF = 0).
Reserved
Loss of clock status. When the oscillator or external clock source is not at the minimum fre-
quency, the loss-of-clock circuit asserts the LOCS bit. This bit is cleared when the oscillator
or external clock source is functioning normally. This bit is reset only on power-on reset.
Writes to this bit have no effect.
0 = No loss of oscillator is currently detected
1 = Loss of oscillator is currently detected
Loss of clock sticky. If, after negation of PORESET, the loss-of-clock circuit detects that the
oscillator or external clock source is not at a minimum frequency, the LOCSS bit is set. LOC-
SS remains set until software clears it by writing a one to it. A write of zero has no effect on
this bit. The reset value is determined during hard reset. The STBUC bit will be set provided
the PLL lock condition is not met when HRESET is asserted, and cleared if the PLL is locked
when HRESET is asserted.
0 = No loss of oscillator has been detected
1 = Loss of oscillator has been detected
SERVE
RE-
U
4
20
Table 8-10 PLPRCR Bit Descriptions
D
U
0
CSRC
CLOCKS AND POWER CONTROL
U
5
21
0 OR 4
0
0
MF
Rev. 15 October 2000
U
6
22
0
0
LPM
U
7
23
0
0
CSR
U
8
24
U
0
Description
LOL-
U
9
RE
25
U
0
SERVE
10
U
RE-
26
D
0
11
U
27
U
0
SERVE
RE-
12
D
U
0
28
U
0
LOCS
DIVF
13
U
0
29
U
0
0x2F C284
MOTOROLA
LOC-
SS
14
U
0
30
U
0
SPLS
8-32
15
LSB
U
0
31
U
0