MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 278

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.8.3.4 Exiting from Power-Down Mode
8.8.3.5 Low-Power Modes Flow
MPC555
USER’S MANUAL
In deep-sleep mode the PLL is disabled. The wake-up time from this mode is up to 500
PLL input frequency clocks. In one-to-one mode the wake-up time may be up to 100
PLL input frequency clocks. For a PLL input frequency of 4 MHz, the wake-up time is
less than 125 µs.
Exit from power-down mode is accomplished through hard reset. External logic should
assert HRESET in response to the TEXPS bit being set and TEXP pin being asserted.
The TEXPS bit is set by an enabled RTC, PIT, time base, or decrementer interrupt.
The hard reset should be asserted for no longer than the time it takes for the power
supply to wake-up in addition to the PLL lock time. When the TEXPS bit is cleared (and
the TEXP signal is negated), assertion of hard reset sets the bit, causes the pin to be
asserted, and causes an exit from power-down low-power mode. Refer to
Alive Power
Figure 8-9
• An interrupt is pending from the interrupt controller
• An interrupt is requested by the RTC, PIT, or time base
• A decrementer exception
/
MPC556
shows the flow among the different power modes.
for more information.
CLOCKS AND POWER CONTROL
Rev. 15 October 2000
8.9.3 Keep
MOTOROLA
8-18