MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 509

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.8.4 SCI Status Register (SCxSR)
SCxSR — SCIx Status Register
MPC555
USER’S MANUAL
RESET:
Bit(s)
MSB
14
15
0
0
SCxSR contains flags that show SCI operating conditions. These flags are cleared ei-
ther by SCIx hardware or by a read/write sequence. The sequence consists of reading
the SCxSR (either the upper byte, lower byte, or the entire half-word) with a flag bit set,
then reading (or writing, in the case of flags TDRE and TC) the SCxDR (either the low-
er byte or the half-word).
The contents of the two 16-bit registers SCxSR and SCxDR appear as upper and low-
er half-words, respectively, when the SCxSR is read into a 32-bit register. An upper
byte access of SCxSR is meaningful only for reads. Note that a word read can simul-
taneously access both registers SCxSR and SCxDR. This action clears the receive
status flag bits that were set at the time of the read, but does not clear the TDRE or
TC flags. To clear TC, the SCxSR read must be followed by a write to register SCxDR
(either the lower byte or the half-word). The TDRE flag in the status register is read-
only.
If an internal SCI signal for setting a status bit comes after the CPU has read the as-
serted status bits but before the CPU has read or written the SCxDR, the newly set
status bit is not cleared. Instead, SCxSR must be read again with the bit set and
SCxDR must be read or written before the status bit is cleared.
/
1
0
MPC556
Name
RWU
SBK
None of the status bits are cleared by reading a status bit while it is
set and then writing zero to that same bit. Instead, the procedure out-
lined above must be followed. Note further that reading either byte of
SCxSR causes all 16 bits to be accessed, and any status bits already
set in either byte are armed to clear on a subsequent read or write of
SCxDR.
2
0
RESERVED
Table 14-24 SCCxR1 Bit Descriptions (Continued)
Receiver wakeup. Refer to
0 = Normal receiver operation (received data recognized).
1 = Wakeup mode enabled (received data ignored until receiver is awakened).
Send break
0 = Normal operation.
1 = Break frame(s) transmitted after completion of current frame.
3
0
QUEUED SERIAL MULTI-CHANNEL MODULE
4
0
5
0
Rev. 15 October 2000
6
0
14.8.7.9 Receiver
TDRE
7
1
NOTE
TC
8
1
Description
RDRF
Wake-Up.
9
0
RAF
10
0
IDLE
11
0
0x30 500C, 0x30 5024
OR
12
0
NF
13
0
MOTOROLA
FE
14
0
14-47
LSB
PF
15
0