MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 123

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.1 RCPU Features
MPC555 / MPC556
USER’S MANUAL
The PowerPC-based RISC processor (RCPU) used in the MPC500 family of micro-
controllers integrates five independent execution units: an integer unit (IU), a load/
store unit (LSU), and a branch processing unit (BPU), floating-point unit (FPU) and in-
teger multiplier divider (IMD). The use of simple instructions with rapid execution times
yields high efficiency and throughput for MPC555 / MPC556-based systems.
Most integer instructions execute in one clock cycle. Instructions can complete out of
order for increased performance; however, the processor makes execution appear se-
quential.
This section provides an overview of the RCPU. For a detailed description of this pro-
cessor, refer to the
Major features of the RCPU include the following:
• High-performance microprocessor
• Five independent execution units and two register files
• Facilities for enhanced system performance
• In-system testability and debugging features
• High instruction and data throughput
— Single clock-cycle execution for many instructions
— Independent LSU for load and store operations
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision opera-
— Thirty-two general-purpose registers (GPRs) for integer operands
— Thirty-two floating-point registers (FPRs) for single- or double-precision oper-
— Programmable big- and little-endian byte ordering
— Atomic memory references
— Condition register (CR) look-ahead operations performed by BPU
— Branch-folding capability during execution (zero-cycle branch execution time)
— Programmable static branch prediction on unresolved conditional branches
— A pre-fetch queue that can hold up to four instructions, providing look-ahead
— Interlocked pipelines with feed-forwarding that control data dependencies in
tions
ands
capability
hardware
RCPU Reference Manual
CENTRAL PROCESSING UNIT
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
SECTION 3
(RCPURM/AD).
MOTOROLA
3-1