MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 393

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.5.3 L-bus Memory Access Violations
11.6 Reservation Support
11.6.1 The Reservation Protocol
11.6.2 L2U Reservation Support
MPC555
USER’S MANUAL
All L-bus slaves have their own access protection logic. For consistency, all storage
access violations have the same termination result. Thus access violations for load/
store accesses started by the RCPU always have the same termination from all
slaves: assertion of the data storage exception. All other L-bus masters cause ma-
chine check exceptions.
The RCPU storage reservation protocol supports a multi-level bus structure. For each
local bus, storage reservation is handled by the local reservation logic. The protocol
tries to optimize reservation cancellation such that a PowerPC processor (RCPU) is
notified of storage reservation loss on a remote bus (U-bus, IMB or external bus) only
when it has issued a stwcx cycle to that address. That is, the reservation loss indica-
tion comes as part of the stwcx cycle.
The reservation protocol operates under the following assumptions:
The L2U is responsible for handling the effects of reservations on the L-bus and the
U-bus. For the L-bus and the U-bus, the L2U detects reservation losses.
The reservation logic in the L2U performs the following functions:
The unit for reservation is one word. A byte or half-word store request by another mas-
ter will clear the reservation flag.
A load-with-reservation request by the CPU updates the reservation address related
to a previous load-with-reservation request and sets the reservation flag for the new
location. A store-with-reservation request by the CPU clears the reservation flag. A
store request by the CPU does not clear the flag. A store request by some other master
to the reservation address clears the reservation flag.
• Each processor has at most 1 reservation flag
• A lwarx instruction sets the reservation flag
• Another lwarx instruction by same processor clears the reservation flag related
• A stwcx instruction by same processor clears the reservation flag
• A store instruction by same processor does not clear the reservation flag
• Some other processor (or other mechanism) store to an address with an existing
• In case the storage reservation is lost, it is guaranteed that stwcx will not modify
• Snoops accesses to all L-bus and U-bus slaves
• Holds one reservation (address) for the core
• Sets the reservation flag when the CPU issues a load-with-reservation request
/
to a previous lwarx instruction and sets again the reservation flag
reservation clears the reservation flag
the storage
MPC556
L-BUS TO U-BUS INTERFACE (L2U)
Rev. 15 October 2000
MOTOROLA
11-7